DSPIC33CK128MP206T-I/MR - 100MHz 128KB DSC | Microchip
MPN: DSPIC33CK128MP206T-I/MR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.9 | $4.90 |
| 10 | $4.6 | $46.00 |
| 100 | $4.36 | $436.00 |
| 500 | $4.1 | $2,050.00 |
| 1,000 | $3.85 | $3,850.00 |
DSPIC33CK128MP206T-I/MR Overview
A digital signal controller combines the compute power of a DSP with the peripheral integration and interrupt responsiveness of a microcontroller. Within the power-management hierarchy, DSCs sit above generic MCUs for control-loop tasks: they execute proportionally-integral-derivative (PID) and predictive control loops for switching power converters and motor drives at loop rates well beyond 100 kHz, where a general-purpose MCU would struggle to close the loop.
Key features include the dsPIC33CK DSC core delivering up to 100 MIPS from a single-core 16-bit modified Harvard architecture, 128 KB of program flash with error-correction code (ECC) and live-update support across two flash partitions, and 16 KB of data SRAM. The peripheral set targets digital power directly: high-resolution PWM with sub-nanosecond edge placement, 12-bit ADCs, and integrated operational amplifiers reduce external component count in current-sense paths.
The dsPIC33CK family is fabricated on a process optimized for 3.0V to 3.6V operation and supports operation from -40C to +125C for the industrial (I) temperature grade used in this MPN. Peripherals such as CAN Flexible Data (CAN FD) make the part suitable for automotive-adjacent and industrial communication topologies, while four DMA channels offload data movement between ADC results, RAM, and communication interfaces.
Typical applications include digital power supplies (LLC, PFC, buck/boost stages), brushless DC and PMSM motor control for industrial drives, high-intensity LED lighting drivers, and CAN FD networked sensing and control nodes.
When designing with this device, plan flash partitioning early: dual-partition live update requires allocating boot and application partitions, and ECC protects both partitions against single-bit faults. Supply decoupling on all VDD/VDDCORE pins and a clean 3.3V rail are required for the 100 MHz core.
This page synthesizes distributor pricing, drop-in family alternatives, comparison data, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for DSPIC33CK128MP206T-I/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CK128MP206T-I/MR (same form factor and footprint) — differing in Package, Operating Temperature, Architecture, Core, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33CK128MP206T-E/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CK128MP206T-H/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CK128MP506T-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
Contact for price
View Datasheet →DSPIC33CK64MP206T-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$1.75 / Unit
View Datasheet →DSPIC33CK256MP206T-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$2.32 / Unit
View Datasheet →DSPIC33CK128MP206T-I/MR Maximum Ratings & Electrical Characteristics
| Core | dsPIC33CK 16-bit DSC core |
| Maximum Clock Frequency | 100 MHz |
| Performance | Up to 100 MIPS |
| Program Memory Size | 128 KB flash |
| Program Memory Type | Dual-partition flash with ECC and live update |
| Data RAM Size | 16 KB SRAM |
| Supply Voltage Range | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +125C |
| Package | 64-QFN (9x9 mm) with exposed pad |
| Mounting Type | Surface Mount |
| ADC Resolution | 12-bit |
| Integrated Peripherals | Op-amps, 12-bit ADCs, high-resolution PWM |
| Communication Interfaces | CAN FD, UART, SPI, I2C |
| DMA Channels | 4 |
| Architecture | Modified Harvard, 16-bit, single-core |
| RoHS Status | Compliant |
DSPIC33CK128MP206T-I/MR 64-qfn (9x9 mm) with exposed pad Pin Configuration Guide
Pin configuration for DSPIC33CK128MP206T-I/MR (64-qfn (9x9 mm) with exposed pad package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33CK128MP206T-I/MR.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33CK128MP206T-I/MR is suitable for 6 applications: Digital Power Supplies, Brushless DC and PMSM Motor Control, CAN FD Industrial Networking Nodes, High-Current LED Lighting Drivers, Advanced Sensing and Control Systems, Safety-Featured Embedded Control.
Digital Power Supplies
The DSPIC33CK128MP206T-I/MR is purpose-built for digitally controlled power converters such as LLC resonant converters, PFC front ends, and synchronous buck/boost stages. Its 100 MHz (100 MIPS) core closes voltage- and current-mode control loops at switching frequencies beyond 100 kHz, while the high-resolution PWM provides sub-nanosecond edge resolution for precise duty-cycle and dead-time control. The integrated 12-bit ADC samples output voltage and inductor current synchronously with the PWM period, and on-chip op-amps amplify low-side shunt-current signals without external amplifiers, reducing BOM cost. Firmware-based control enables adaptive compensation and live-update firmware changes via the dual-partition ECC flash.
Recommended
Brushless DC and PMSM Motor Control
Field-oriented control (FOC) of BLDC and PMSM motors requires fast current-loop execution, precisely timed gate signals, and accurate current sensing - all strengths of the DSPIC33CK128MP206T-I/MR. The 100 MHz core executes Clarke/Park transforms and PI current loops at multiples of the PWM frequency, while the high-resolution PWM generates complementary outputs with hardware dead-band insertion for the three-phase inverter. The 12-bit ADC samples phase currents mid-PWM via trigger synchronization, and integrated op-amps condition low-side shunt signals. CAN FD connectivity supports networked industrial drives, and the -40C to +125C industrial grade covers factory floor environments.
Recommended
CAN FD Industrial Networking Nodes
With integrated CAN Flexible Data (CAN FD), the DSPIC33CK128MP206T-I/MR serves as an intelligent node on industrial and automotive-adjacent networks running data rates beyond classic CAN's 1 Mbps. The 128 KB dual-partition ECC flash holds the application plus a full CAN FD stack and bootloader, while 16 KB of RAM buffers message objects. DMA channels move CAN payloads between the peripheral and SRAM without CPU intervention, preserving core bandwidth for control or signal-processing tasks. The industrial -40C to +125C temperature grade and 3.0V to 3.6V supply suit factory automation, HVAC controllers, and building-management nodes.
Recommended
High-Current LED Lighting Drivers
Digital LED drivers benefit from the DSPIC33CK128MP206T-I/MR's high-resolution PWM, which dims and color-mixes high-brightness LED strings with precise pulse widths at switching frequencies above the audible range. The 100 MHz core implements average-current-mode control for boost or buck LED drivers, and the 12-bit ADC with PWM-synchronized sampling feeds the feedback loop. Integrated op-amps amplify current-shunt signals directly, and multiple PWM channels independently control several LED strings for RGBW luminaires. Dual-partition flash with ECC allows field firmware updates for new dimming curves or color profiles without service intervention.
Recommended
Advanced Sensing and Control Systems
Sensor front ends and closed-loop industrial controllers use the DSPIC33CK128MP206T-I/MR's combination of fast analog acquisition and DSP-class computation. The 12-bit ADC with DMA streams multi-channel sensor data to the 16 KB SRAM while the 100 MHz core applies digital filtering, FFTs, or control algorithms in real time. Integrated op-amps buffer and amplify signals from thermistors, pressure sensors, or current transformers. The dual-partition ECC flash supports live firmware updates on deployed equipment, and the -40C to +125C range plus RoHS-compliant 64-QFN (9x9 mm) packaging fit compact industrial and instrumentation form factors.
Recommended
Safety-Featured Embedded Control
The DSPIC33CK128MP206T-I/MR is identified by DigiKey as part of the dsPIC33CK Functional Safety (FuSa) offering, making it appropriate for control systems that need a path to safety-related certification. Flash ECC protects program memory against single-bit faults, and memory built-in self-test (MBIST) on the data SRAM supports diagnostic coverage requirements in IEC 61508-aligned designs. The 100 MHz core provides deterministic single-cycle execution for safety-critical loops, while CAN FD links the controller to plant-wide safety networks. Microchip provides safety documentation packages through its FuSa program to support integrator qualification efforts.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK128MP206T-I/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK128MP206T-E/MR | DSPIC33CK128MP206T-H/MR | DSPIC33CK128MP506T-I/MR | DSPIC33CK64MP206T-I/MR |
|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Speed | 100 MHz (100 MIPS) | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Flash Memory | 128 KB | 128 KB | 128 KB | 512 KB | 64 KB |
| Temperature Range | -40C to +125C (I grade) | Extended grade (E) | H grade | -40C to +125C (I grade) | -40C to +125C (I grade) |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Key Peripherals | 12-bit ADC, op-amps, Hi-Res PWM, CAN FD | 12-bit ADC, op-amps, Hi-Res PWM, CAN FD | 12-bit ADC, op-amps, Hi-Res PWM, CAN FD | 12-bit ADC, op-amps, Hi-Res PWM, CAN FD | 12-bit ADC, op-amps, Hi-Res PWM, CAN FD |
Key Differentiators
- Dual-partition flash with ECC and live update (vs DSPIC33CK64MP206T-I/MR)
- Industrial temperature grade at standard pricing (vs DSPIC33CK128MP206T-E/MR)
- Flash capacity scalability on one PCB (vs DSPIC33CK128MP506T-I/MR)
Design Notes
The dsPIC33CK core requires a clean 3.0V-3.6V supply with tight decoupling on every VDD and VDDCORE pin of the 64-QFN package. Estimated: at 100 MHz the core draws on the order of tens of milliamps; place 100 nF ceramic capacitors at each supply pin pair plus one bulk 10 uF capacitor near the package. Never leave any VSS pin unconnected - the ICSP programming requirement explicitly mandates all VDD and VSS pins be connected, and floating grounds cause erratic flash programming and ADC noise.
When using ICSP for programming and debugging, remember that the device has multiple PGECx/PGEDx pin pairs. You must use a matched pair: if PGEC2 is wired to the programmer's ICSPCLK, then PGED2 must carry ICSPDAT. Mixing pairs from different sets causes programming failures. Route the chosen pair away from high-dV/dt switch nodes if the board contains power electronics, since ICSP lines are sensitive during debug sessions.
Exploit the exposed pad on the 9x9 mm QFN: solder it to a grounded copper pour with an array of vias to improve thermal dissipation and reduce ground impedance - important because ADC accuracy and EMI in digital power designs depend on a low-noise reference ground. Keep the high-resolution PWM outputs short to gate-driver inputs, and separate analog ground for the op-amp/ADC signals from power-switching ground, tying them at a single star point near the device.
Plan dual-partition flash allocation at project start. Live-update firmware requires the boot and application code to fit in separate partitions of the 128 KB flash with ECC. If your firmware plus bootloader approaches 64 KB per partition, select the 512 KB DSPIC33CK128MP506T-I/MR instead - it is pin-to-pin compatible, so no PCB change is needed. Also enable the memory built-in self-test (MBIST) in startup code if your product targets functional-safety documentation.
Compliance Information
RoHS compliance per distributor listings (LCSC/DigiKey). AEC-Q100 qualification not stated in provided data for this exact MPN; the family is marketed with Functional Safety (FuSa) support per DigiKey listing. Other values not found in provided data.
