DSPIC33CK128MP506T-I/MR - 16-bit 100MHz DSC 128KB Flash | Microchip
MPN: DSPIC33CK128MP506T-I/MR ✓ Active| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
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| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
DSPIC33CK128MP506T-I/MR Overview
A digital signal controller combines the computational throughput of a digital signal processor with the integrated peripherals and control architecture of a microcontroller. Within the power management hierarchy of embedded systems, a DSC such as the dsPIC33CK128MP506 sits between general-purpose MCUs and dedicated DSPs, making it the preferred device class for closed-loop control loops such as digital power conversion, motor control, and advanced sensing where deterministic interrupt latency and fast math matter.
Key differentiating features include a DC to 100 MIPS instruction execution rate, a high-resolution PWM with 250 ps edge resolution for precision power-stage switching, three integrated operational amplifiers and three analog comparators that offload external analog signal conditioning, and CAN Flexible Data (CAN FD) for modern automotive and industrial networking. The modified Harvard architecture with DSP engine supports single-cycle MAC and hardware division for control algorithms.
Technical depth: the device integrates up to 128KB of program Flash with Error Correction Code (ECC) and a dual-partition live-update scheme for field firmware upgrades without downtime, plus Memory Built-In Self-Test (MBIST) supporting functional-safety development. The Peripheral Trigger Generator (PTG) automates peripheral-to-peripheral sequencing to reduce CPU loading in time-critical loops.
Typical applications include digitally controlled switch-mode power supplies (AC-DC, DC-DC), PFC stages, brushless DC and PMSM motor drives, and CAN FD-connected industrial control nodes where the on-chip op-amps feed high-speed PWM control loops.
Design consideration: budget the exposed thermal pad of the 64-QFN (MR) package with a solid ground plane array of thermal vias; at 100 MHz core operation, thermal performance depends directly on pad solder coverage.
This page synthesizes distributor inventory data, same-family drop-in variants, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33CK128MP506T-I/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CK128MP506T-I/MR (same form factor and footprint) — differing in Package, Core, Operating Temperature, CAN Interface, RAM.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33CK128MP506-E/MR
✅ Drop-In✓ In Stock
$4.42 / Unit
View Datasheet →DSPIC33CK128MP506T-E/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CK128MP506T-H/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CK64MP506T-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$2.68 / Unit
View Datasheet →DSPIC33CK256MP506T-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.98 / Unit
View Datasheet →DSPIC33CK32MP506T-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$1.75 / Unit
View Datasheet →DSPIC33CK128MP506T-I/MR Maximum Ratings & Electrical Characteristics
| Core | dsPIC33CK 16-bit DSC core |
| Core Speed | 100 MHz (up to 100 MIPS) |
| Program Memory (Flash) | 128 KB with ECC, dual-partition live update |
| Data SRAM | 16 KB with MBIST |
| Operating Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (I grade) |
| Package | 64-QFN (MR) 9x9 mm, exposed pad |
| PWM Resolution | 250 ps (high-resolution PWM) |
| Integrated Op-Amps | 3 |
| Integrated Comparators | 3 |
| CAN | CAN FD |
| Peripherals | PTG (Peripheral Trigger Generator) |
| Architecture | Modified Harvard with DSP engine |
| Mounting Type | Surface Mount |
| Pin Pitch | 0.5 mm |
| Data Bus Width | 16 bit |
| Product Family | dsPIC33CK |
DSPIC33CK128MP506T-I/MR 64-qfn (mr) 9x9 mm, exposed pad Pin Configuration Guide
Pin configuration for DSPIC33CK128MP506T-I/MR (64-qfn (mr) 9x9 mm, exposed pad package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33CK128MP506T-I/MR.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33CK128MP506T-I/MR is suitable for 6 applications: Digital Switch-Mode Power Supplies, Brushless DC and PMSM Motor Control, CAN FD Industrial and Automotive Nodes, Advanced Sensing and Control Systems, Wireless Charging and Resonant Power Conversion, Test and Measurement Instrumentation.
Digital Switch-Mode Power Supplies
The DSPIC33CK128MP506T-I/MR is purpose-built for digitally controlled AC-DC and DC-DC power conversion. Its 250 ps high-resolution PWM achieves fine duty-cycle resolution for precision regulation of LLC, flyback, and PFC stages, while the 100 MHz / 100 MIPS DSP core executes control loops with single-cycle MAC operations at switching frequencies well above 100 kHz. The three integrated op-amps can condition current-sense signals without external amplifiers, and the three analog comparators support hardware-based cycle-by-cycle overcurrent protection with latency far below any software loop. Running from a 3.0V to 3.6V rail with ECC-protected Flash and dual-partition live update, the controller can be field-upgraded without taking the power supply offline, which is valuable in server and telecom power where uptime is contractual.
Recommended
Brushless DC and PMSM Motor Control
For sensorless and sensored BLDC/PMSM drives, the DSPIC33CK128MP506T-I/MR combines the computational throughput needed for field-oriented control (FOC) with an analog front-end that reduces bill-of-material cost. The 100 MHz core computes FOC transformations at multi-kHz loop rates, while the three on-chip op-amps amplify shunt-resistor phase currents directly into the ADC path. The 250 ps PWM resolution minimizes current ripple and audible noise at low speeds. Three comparators provide hardware overcurrent trip without CPU intervention. The 64-QFN (MR) package integrates all these functions in a 9x9 mm footprint, and CAN FD connects the drive to industrial or automotive networks. For applications above +85C ambient, the pin-compatible -E/MR variant extends rating to +125C with AEC-Q100 qualification.
Recommended
CAN FD Industrial and Automotive Nodes
The integrated CAN Flexible Data (CAN FD) module makes the DSPIC33CK128MP506T-I/MR a strong controller for industrial gateways, sensor aggregation nodes, and automotive body/powertrain controllers. CAN FD raises payload throughput to up to 64-byte frames at higher arbitration-free data rates than classical CAN, and the DSC's 100 MIPS DSP core can simultaneously run local control loops and protocol stacks without saturating. With -40C to +85C industrial rating (or the AEC-Q100 -E variant for automotive), the device suits harsh environments. The PTG (Peripheral Trigger Generator) automates timed peripheral sequencing such as periodic ADC sampling with PWM synchronization, offloading the CPU. Dual-partition Flash live update allows firmware deployment over the network without downtime, an important serviceability feature in distributed automation systems.
Recommended
Advanced Sensing and Control Systems
The DSPIC33CK128MP506T-I/MR excels in high-precision sensing platforms such as power analyzers, battery test equipment, and process-control transmitters. The 16-bit DSP core with modified Harvard architecture executes digital filtering and calibration math quickly, while the three op-amps provide on-chip signal conditioning for bridge sensors, shunt-based current measurement, and pH/pressure front-ends. MBIST and ECC Flash support functional-safety (FuSa) oriented designs where memory integrity must be demonstrated. The PTG enables deterministic, CPU-independent acquisition sequences - useful for interleaved multi-channel sampling. With 128KB of Flash, complex calibration tables, compensation routines, and communication stacks coexist with headroom. The 64-QFN 9x9 mm exposed-pad package supports dense multi-channel board layouts, and live update allows calibration firmware to be updated in the field.
Recommended
Wireless Charging and Resonant Power Conversion
Resonant converters, including wireless power transmitters and LLC stages, demand extremely fine PWM phase and frequency control - exactly what the DSPIC33CK128MP506T-I/MR's 250 ps high-resolution PWM delivers. The 100 MHz core runs frequency-tracking control loops that keep the resonant tank at optimum efficiency under varying load and coupling conditions, while the three comparators implement hardware zero-crossing detection for synchronous rectification timing. The integrated op-amps condition current and voltage sense signals for the DSP-based control loop. Dual-partition live update lets manufacturers deploy coil-compensation firmware updates in installed base units. The 64-QFN (MR) package's exposed pad dissipates heat reliably at sustained 100 MHz operation when properly thermally via-connected, supporting compact transmitter designs for consumer and industrial wireless charging.
Recommended
Test and Measurement Instrumentation
Bench instruments, electronic loads, and programmable power modules benefit from the DSPIC33CK128MP506T-I/MR's blend of control performance and integration. The 100 MIPS DSP core executes measurement averaging, PID servo loops for electronic-load FET biasing, and communication protocol handling concurrently. The 250 ps PWM provides fine-resolution DAC-like setpoint generation via filtered PWM, while the three op-amps and three comparators support fast protection trip levels settable in hardware. CAN FD enables modular instrument backbones where multiple measurement cards report over a single robust bus. The 64-QFN 9x9 mm layout suits high-density cards, and the industrial -40C to +85C rating covers bench-to-field deployment. Live-update Flash partitions allow feature firmware to be upgraded by service software without returning the unit to the factory.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK128MP506T-I/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK128MP506-E/MR | DSPIC33CK128MP506T-E/MR | DSPIC33CK128MP506T-H/MR | DSPIC33CK64MP506T-I/MR | DSPIC33CK256MP506T-I/MR |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 64-QFN (MR) 9x9 mm | 64-QFN (MR) - same | 64-QFN (MR) - same | 64-QFN (MR) - same | 64-QFN (MR) - same | 64-QFN (MR) - same |
| Program Flash | 128 KB with ECC | 128 KB with ECC | 128 KB with ECC | 128 KB | 64 KB | 256 KB |
| SRAM | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB | 24 KB |
| Key Peripherals | 250 ps PWM, 3 op-amps, 3 comparators, CAN FD, PTG | Identical | Identical | Identical | Identical | Identical |
Key Differentiators
- Extended temperature and automotive qualification (vs DSPIC33CK128MP506-E/MR)
- Larger Flash headroom in same footprint (vs DSPIC33CK256MP506T-I/MR)
- Cost optimization without re-layout (vs DSPIC33CK64MP506T-I/MR)
Design Notes
The 64-QFN (MR) exposed pad is the primary heat-removal path and is tied to VSS. Connect it to the ground plane through an array of at least 4x4 thermal vias (approximately 0.3 mm drill, 1.0 mm pitch) with adequate paste coverage in the pad stencil - typically 50-70% coverage split across multiple apertures to prevent voiding. At the 100 MHz core speed, insufficient solder coverage on the exposed pad is the most common cause of excessive junction temperature in dsPIC33CK designs. Verify junction temperature against the -40C to +85C ambient rating under worst-case load. Estimated: via-array thermal resistance dominates, so copper area under the QFN should extend at least 5 mm beyond the package outline.
Place a 100 nF ceramic decoupling capacitor at each VDD/VSS pin pair, within 2 mm of the pin, plus at least one bulk 10 uF capacitor near the device. The 3.0V to 3.6V supply should be locally regulated if the board runs from a 5V or 24V bus. Keep the high-resolution PWM output traces away from the analog front-end routing that feeds the on-chip op-amps, and use a solid ground plane referenced to the exposed pad to minimize ground bounce between the digital core and analog peripherals.
Do not exceed the 3.6V maximum supply rating - the dsPIC33CK is a 3.3V-only family and has no 5V-tolerant configuration. When substituting the -I grade with the -E grade, confirm your firmware's configuration words match, since some temperature grades have different electrical characteristics at the frequency/voltage extremes. When using dual-partition live update, remember that both partitions must be sized in linker scripts before production - re-partitioning after deployment requires a full-chip erase. Verify peripheral pin selection (PPS) mappings after any migration between family members.
Compliance Information
The -I grade itself is not AEC-Q100 qualified; the AEC-Q100 qualified -E grade variant (DSPIC33CK128MP506T-E/MR) is noted as AEC-Q100 qualified per Microchip USA product data. RoHS/REACH status not stated in provided web data - verify on the Microchip product page.
