DSPIC33CK128MP206-E/MR - 100MHz 128KB DSC CAN FD | Microchip
MPN: DSPIC33CK128MP206-E/MR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.45 | $2.45 |
| 10 | $2.36 | $23.60 |
| 100 | $2.25 | $225.00 |
| 500 | $2.15 | $1,075.00 |
| 1,000 | $2.05 | $2,050.00 |
DSPIC33CK128MP206-E/MR Overview
A digital signal controller combines the computational throughput of a digital signal processor (DSP) with the peripheral integration and deterministic control of a microcontroller. Within the embedded control hierarchy, the dsPIC33CK sits above general-purpose 8-bit MCUs and alongside dedicated DSPs, targeting closed-loop power conversion, motor control, and advanced sensing applications that demand high-resolution timing and fast analog-to-digital conversion in a single silicon device.
Key differentiating features include a modified Harvard architecture executing up to 100 MIPS from a single-core pipeline, 250 ps effective PWM resolution from the High-Resolution PWM module, dual 12-bit ADCs, and integrated CAN Flexible Data (CAN FD) for industrial and automotive networking. On-chip operational amplifiers reduce external component count in current-sense loops, and functional safety (FuSa) documentation support eases certification in safety-relevant designs.
Technical depth: the flash is organized in dual partitions with ECC and Live Update capability, enabling field firmware updates without a second external memory. Memory Built-in Self-Test (MBIST) on the SRAM supports safety analyses. The 250 ps PWM edge resolution allows duty-cycle granularity far beyond a simple 100 MHz counter, critical for peak-current-mode and phase-shifted converter topologies.
Typical applications include digital power supplies (PFC, LLC, totem-pole converters), PMSM/BLDC and ACIM motor drives with sensorless field-oriented control, automotive auxiliary systems on the -E AEC-Q100 temperature grade, and CAN FD-networked industrial control nodes.
Design consideration: the device operates from a tight 3.0V to 3.6V supply, so a local 3.3V regulator with solid decoupling on all VDD/VDDCORE pairs is essential; the -E extended grade (-40C to +125C ambient) allows derating margins that the standard -I grade does not.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not consolidated in the manufacturer datasheet, with pricing as of 2026-09-22.
Drop-in alternatives for DSPIC33CK128MP206-E/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CK128MP206-E/MR (same form factor and footprint) — differing in Operating Temperature, Package, Data SRAM, Program Flash, Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33CK128MP206-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$2.23 / Unit
View Datasheet →DSPIC33CK256MP206-E/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$2.52 / Unit
View Datasheet →DSPIC33CK64MP206-E/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
Contact for price
View Datasheet →DSPIC33CK128MP206T-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.85 / Unit
View Datasheet →DSPIC33CK128MP206-E/MR Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33CK DSC, modified Harvard |
| Maximum CPU Speed | 100 MHz (100 MIPS) |
| Program Flash | 128 KB, dual-partition with ECC and Live Update |
| Data SRAM | 16 KB with MBIST |
| Supply Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +125C (E grade) |
| Package | 64-QFN (9x9 mm), package code MR |
| PWM Resolution | 250 ps (High-Resolution PWM) |
| ADC | Dual 12-bit ADCs |
| CAN Interface | CAN FD |
| Qualification | AEC-Q100 automotive qualified |
| Functional Safety Support | Yes (FuSa package) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Packaging | Tube |
DSPIC33CK128MP206-E/MR 64-qfn (9x9 mm), package code mr Pin Configuration Guide
Pin configuration for DSPIC33CK128MP206-E/MR (64-qfn (9x9 mm), package code mr package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33CK128MP206-E/MR.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33CK128MP206-E/MR is suitable for 6 applications: Digital Power Supplies, Motor Control Drives, Automotive Auxiliary Systems, Industrial CAN FD Control Nodes, Advanced Sensing and Control, Lighting and RF-ballast Control.
Digital Power Supplies
The DSPIC33CK128MP206-E/MR fits digital power conversion because its 250 ps high-resolution PWM resolves duty-cycle steps far finer than a standard 10 ns counter tick, while dual 12-bit ADCs can sample current and voltage feedback nearly simultaneously for the control loop. In PFC, LLC, and totem-pole PFC stages, the on-chip analog comparators support cycle-by-cycle current limiting without CPU intervention. Placed as the sole controller between the feedback dividers and gate drivers, it executes voltage-mode or current-mode compensation at 100 MIPS with deterministic interrupt latency. The trade-off versus analog control is firmware complexity, but the payoff is programmability across output voltages and soft-start profiles on one PCB.
Recommended
Motor Control Drives
Sensorless field-oriented control (FOC) of PMSM and BLDC motors is a primary use case for the DSPIC33CK128MP206-E/MR: the 100 MHz core executes FOC loops at 10-20 kHz carrier rates with headroom, the high-resolution PWM generates complementary outputs with sub-ns effective dead-time trim, and dual ADCs synchronize to PWM triggers to sample phase currents at the midpoint of the PWM period, minimizing switching-noise corruption. Integrated on-chip op amps buffer shunt-current signals, cutting external component count. The -E grade (-40C to +125C) suits pump, fan, and traction-adjacent enclosures with limited cooling. One consideration: flash-based FOC tables and field-weakening routines should leave margin within the 128 KB program space.
Recommended
Automotive Auxiliary Systems
As an AEC-Q100 qualified part with a -40C to +125C operating range, the DSPIC33CK128MP206-E/MR targets automotive auxiliary electronic modules - blower controllers, valve and pump drivers, lighting ballasts, and actuator nodes - that sit outside the safety-critical powertrain domain but still demand automotive-grade reliability. The integrated CAN FD interface connects the module to gateway ECUs at data-phase rates up to 8 Mbit/s per the standard, carrying richer diagnostic payloads than classical CAN. Microchip's Functional Safety (FuSa) package supplies safety manuals and diagnostic coverage documentation that support tier-1 ISO 26262 analyses. Confirm the specific AEC-Q100 grade level and PPAP availability with Microchip for production programs.
Recommended
Industrial CAN FD Control Nodes
Factory automation nodes benefit from the DSPIC33CK128MP206-E/MR's combination of a 100 MIPS control core and an on-chip CAN FD controller, which removes the need for an external CAN controller and its associated latency. A single device can close a servo or heater loop at kilohertz rates while streaming diagnostics over a 64-byte-payload CAN FD network at data-phase bit rates far above classical CAN. The 250 ps PWM resolution suits high-frequency converter and inverter stages inside the node, and the peripheral pin select (PPS) system lets designers route UARTs and SPI around board constraints. The -E extended temperature grade tolerates cabinet environments where -I parts would derate.
Recommended
Advanced Sensing and Control
High-performance sensing front ends use the DSPIC33CK128MP206-E/MR where fast, accurate acquisition meets control output. The dual 12-bit ADCs support simultaneous sampling of two channels with configurable sample-and-hold, and the SRAM includes Memory Built-in Self-Test (MBIST) for applications where data integrity must be argued in a safety case. On-chip operational amplifiers condition low-level sensor signals (shunts, bridge outputs) before conversion, while DSP MAC instructions execute filtering and FFT blocks in real time at 100 MIPS. Typical systems include power-quality analyzers, weigh scales with dynamic compensation, and ultrasonic flow meters. The tight 3.0V to 3.6V supply requires a clean, low-noise analog rail for full ADC accuracy.
Recommended
Lighting and RF-ballast Control
High-intensity discharge, LED ballast, and wireless-charging topologies all require phase-controlled resonant bridges, which the DSPIC33CK128MP206-E/MR drives directly with its high-resolution PWM: 250 ps edge granularity allows precise burst-mode and phase-shift control at hundreds of kilohertz, keeping ZVS windows stable as load changes. Fast analog comparators plus the DAC references implement instant overcurrent shutdown between CPU cycles. The 64-pin package provides enough PWM channels to run multiple independent lamp or coil channels from one controller, consolidating what previously required two MCUs. Designers should budget for firmware-based protection logic since the 128 KB flash must hold both the resonant control law and fault-management state machines.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK128MP206-E/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK128MP206-I/MR | DSPIC33CK256MP206-E/MR | DSPIC33CK64MP206-E/MR |
|---|---|---|---|---|
| Package | 64-QFN (9x9 mm), MR | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 100 MHz (100 MIPS) | 100 MHz (100 MIPS) | 100 MHz (100 MIPS) | 100 MHz (100 MIPS) |
| Program Flash | 128 KB | 128 KB | 256 KB | 64 KB |
| SRAM | 16 KB | 16 KB | 24 KB | 16 KB |
| Temperature Range | -40C to +125C (E grade) | -40C to +85C (I grade) | -40C to +125C (E grade) | -40C to +125C (E grade) |
| PWM Resolution | 250 ps | 250 ps | 250 ps | 250 ps |
| CAN Interface | CAN FD | CAN FD | CAN FD | CAN FD |
Key Differentiators
- Extended -40C to +125C temperature range with AEC-Q100 qualification (vs DSPIC33CK128MP206-I/MR)
- 250 ps High-Resolution PWM (vs DSPIC33CK64MP206-E/MR)
- Cost-efficient 128 KB sweet spot (vs DSPIC33CK256MP206-E/MR)
Design Notes
Supply the DSPIC33CK128MP206-E/MR from a clean 3.0V-3.6V rail (nominal 3.3V). Place 100 nF ceramic decoupling capacitors on every VDD pin within 2 mm of the pad, one bulk 10 uF per rail, and dedicate a separate RC-filtered AVDD (for example 10 ohm + 1 uF) for the analog supply to preserve 12-bit ADC accuracy. VDDCORE requires its specified decoupling capacitor for the internal core regulator - do not omit it or the device will not start. Estimated: a 100 MIPS code workload drawing tens of mA keeps total dissipation well under 100 mW, so no heatsinking is needed.
Route high-resolution PWM outputs (250 ps edge resolution) as short, matched traces to the gate drivers; parasitic inductance and mismatch quickly erode the sub-nanosecond timing advantage the module provides. Keep the ADC reference (VREF+/AVSS) traces away from PWM and CAN FD switching lines, and use a solid ground plane under the QFN center pad - solder the exposed thermal/electrical pad to the plane array with multiple vias for both grounding and thermal relief. Follow Microchip's dsPIC33CK family layout guidelines in the datasheet PCB section.
Three pitfalls recur with this family. First, confusing the -E and -I temperature grades: the -I part is not rated beyond +85C ambient, which fails only after enclosure heating is accounted for - the -E grade here covers -40C to +125C. Second, dual-partition flash with Live Update changes linker memory maps; using a single-partition project file on dual-partition silicon causes mislinked code. Third, peripheral pin select (PPS) must explicitly lock (set the PPS lock bit) after mapping pins, or a runaway pointer can silently remap PWM outputs - a real hazard in power electronics.
The CAN FD interface should use a transceiver qualified for the target data-phase rate (for example 2-8 Mbit/s) with proper termination (120 ohm split termination is common) and a common-mode choke at the connector. Keep the crystal or internal-FSO-based clock references short; if using the internal fast RC oscillator for the 100 MHz PLL path, verify jitter against your PWM dead-time budget in high-frequency converter designs. Follow Microchip CAN FD timing calculation worksheets when programming bit-time segments.
Compliance Information
AEC-Q100 automotive qualification and RoHS compliance indicated by distributor listings (DigiKey, datasheets.com). REACH, halogen-free, and conflict minerals status not stated in provided data.
