EP1K10TC144-3 - 10K Gate ACEX-1K FPGA 144-LQFP | Intel / Altera
MPN: EP1K10TC144-3 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.4 | $18.40 |
| 10 | $16.1 | $161.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.75 | $6,375.00 |
| 1,000 | $11.55 | $11,550.00 |
Drop-in alternatives for EP1K10TC144-3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1K10TC144-3N
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View Datasheet βEP1K10TC144-2N
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View Datasheet βEP1K10TC144-2
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View Datasheet βEP1K10TC144-1N
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View Datasheet βEP1K10TC144-1
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View Datasheet βEP1K30TC144-3
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View Datasheet βEP1K10TC144-3 Maximum Ratings & Electrical Characteristics
| Family | ACEX-1K |
| Logic Elements / Cells | 576 |
| Typical Gates | 10,000 |
| Embedded RAM Bits | 12,288 |
| Embedded Array Blocks (EABs) | 4 |
| User I/O Pins | 92 |
| Speed Grade | -3 |
| Maximum Internal Frequency | 200 MHz |
| Core Voltage (VCCINT) | 2.5 V |
| I/O Voltage (VCCIO) | 3.3 V |
| Process Technology | 0.22 Β΅m CMOS |
| Package | 144-LQFP (TQFP) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
| Configuration Method | SRAM, JTAG IEEE 1149.1 |
EP1K10TC144-3 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | VCCIO1 β I/O bank 1 supply (3.3V) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | VCCINT β Core supply (2.5V) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | VCCIO2 β I/O bank 2 supply (3.3V) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | GND β Ground |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | VCCINT β Core supply (2.5V) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O pin (bank 3) |
| Pin 26 | I/O β User I/O pin (bank 3) |
| Pin 27 | VCCIO3 β I/O bank 3 supply (3.3V) |
| Pin 28 | I/O β User I/O pin (bank 3) |
| Pin 29 | I/O β User I/O pin (bank 3) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin (bank 3) |
| Pin 32 | I/O β User I/O pin (bank 3) |
| Pin 33 | VCCINT β Core supply (2.5V) |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O pin (bank 4) |
| Pin 38 | I/O β User I/O pin (bank 4) |
| Pin 39 | VCCIO4 β I/O bank 4 supply (3.3V) |
| Pin 40 | I/O β User I/O pin (bank 4) |
| Pin 41 | I/O β User I/O pin (bank 4) |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O pin (bank 4) |
| Pin 44 | I/O β User I/O pin (bank 4) |
| Pin 45 | VCCINT β Core supply (2.5V) |
| Pin 46 | I/O β User I/O pin (bank 4) |
| Pin 47 | I/O β User I/O pin (bank 4) |
| Pin 48 | GND β Ground |
| Pin 49 | I/O β User I/O pin (bank 4) |
| Pin 50 | I/O β User I/O pin (bank 4) |
| Pin 51 | I/O β User I/O pin (bank 4) |
| Pin 52 | I/O β User I/O pin (bank 4) |
| Pin 53 | VCCIO4 β I/O bank 4 supply (3.3V) |
| Pin 54 | I/O β User I/O pin (bank 4) |
| Pin 55 | I/O β User I/O pin (bank 4) |
| Pin 56 | GND β Ground |
| Pin 57 | I/O β User I/O pin (bank 4) |
| Pin 58 | I/O β User I/O pin (bank 4) |
| Pin 59 | VCCINT β Core supply (2.5V) |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | I/O β User I/O pin (bank 4) |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β User I/O pin (bank 3) |
| Pin 64 | I/O β User I/O pin (bank 3) |
| Pin 65 | VCCIO3 β I/O bank 3 supply (3.3V) |
| Pin 66 | I/O β User I/O pin (bank 3) |
| Pin 67 | I/O β User I/O pin (bank 3) |
| Pin 68 | GND β Ground |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | I/O β User I/O pin (bank 3) |
| Pin 71 | VCCINT β Core supply (2.5V) |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | I/O β User I/O pin (bank 3) |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β User I/O pin (bank 3) |
| Pin 76 | I/O β User I/O pin (bank 3) |
| Pin 77 | VCCIO3 β I/O bank 3 supply (3.3V) |
| Pin 78 | I/O β User I/O pin (bank 3) |
| Pin 79 | I/O β User I/O pin (bank 3) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β User I/O pin (bank 3) |
| Pin 82 | I/O β User I/O pin (bank 3) |
| Pin 83 | VCCINT β Core supply (2.5V) |
| Pin 84 | I/O β User I/O pin (bank 3) |
| Pin 85 | I/O β User I/O pin (bank 3) |
| Pin 86 | GND β Ground |
| Pin 87 | I/O β User I/O pin (bank 2) |
| Pin 88 | I/O β User I/O pin (bank 2) |
| Pin 89 | VCCIO2 β I/O bank 2 supply (3.3V) |
| Pin 90 | I/O β User I/O pin (bank 2) |
| Pin 91 | I/O β User I/O pin (bank 2) |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β User I/O pin (bank 2) |
| Pin 94 | I/O β User I/O pin (bank 2) |
| Pin 95 | VCCINT β Core supply (2.5V) |
| Pin 96 | I/O β User I/O pin (bank 2) |
| Pin 97 | I/O β User I/O pin (bank 2) |
| Pin 98 | GND β Ground |
| Pin 99 | I/O β User I/O pin (bank 2) |
| Pin 100 | I/O β User I/O pin (bank 2) |
| Pin 101 | VCCIO2 β I/O bank 2 supply (3.3V) |
| Pin 102 | I/O β User I/O pin (bank 2) |
| Pin 103 | I/O β User I/O pin (bank 2) |
| Pin 104 | GND β Ground |
| Pin 105 | I/O β User I/O pin (bank 2) |
| Pin 106 | I/O β User I/O pin (bank 2) |
| Pin 107 | VCCINT β Core supply (2.5V) |
| Pin 108 | I/O β User I/O pin (bank 2) |
| Pin 109 | I/O β User I/O pin (bank 2) |
| Pin 110 | GND β Ground |
| Pin 111 | I/O β User I/O pin (bank 1) |
| Pin 112 | I/O β User I/O pin (bank 1) |
| Pin 113 | VCCIO1 β I/O bank 1 supply (3.3V) |
| Pin 114 | I/O β User I/O pin (bank 1) |
| Pin 115 | I/O β User I/O pin (bank 1) |
| Pin 116 | GND β Ground |
| Pin 117 | I/O β User I/O pin (bank 1) |
| Pin 118 | I/O β User I/O pin (bank 1) |
| Pin 119 | VCCINT β Core supply (2.5V) |
| Pin 120 | I/O β User I/O pin (bank 1) |
| Pin 121 | I/O β User I/O pin (bank 1) |
| Pin 122 | GND β Ground |
| Pin 123 | I/O β User I/O pin (bank 1) |
| Pin 124 | I/O β User I/O pin (bank 1) |
| Pin 125 | VCCIO1 β I/O bank 1 supply (3.3V) |
| Pin 126 | I/O β User I/O pin (bank 1) |
| Pin 127 | I/O β User I/O pin (bank 1) |
| Pin 128 | GND β Ground |
| Pin 129 | I/O β User I/O pin (bank 1) |
| Pin 130 | I/O β User I/O pin (bank 1) |
| Pin 131 | VCCINT β Core supply (2.5V) |
| Pin 132 | I/O β User I/O pin (bank 1) |
| Pin 133 | I/O β User I/O pin (bank 1) |
| Pin 134 | GND β Ground |
| Pin 135 | TDI β JTAG Test Data In |
| Pin 136 | TMS β JTAG Test Mode Select |
| Pin 137 | TCK β JTAG Test Clock |
| Pin 138 | nSTATUS β Configuration status |
| Pin 139 | nCONFIG β Configuration control (active low) |
| Pin 140 | DCLK β Configuration clock |
| Pin 141 | CONF_DONE β Configuration done indicator |
| Pin 142 | TDO β JTAG Test Data Out |
| Pin 143 | MSEL0 β Configuration mode select 0 |
| Pin 144 | MSEL1 β Configuration mode select 1 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1K10TC144-3 is suitable for 6 applications: Legacy Bus Interface Bridging, Industrial Control Logic Replacement, Telecom Glue Logic and Protocol Conversion, Embedded System Peripheral Expansion, Test Equipment Custom Instrumentation, Legacy Design Maintenance and Repair.
Legacy Bus Interface Bridging
The EP1K10TC144-3's 92 user I/O pins and 12,288 bits of block RAM make it well suited for legacy bus interface bridging between microprocessors, memory, and peripherals such as ISA-to-PCI, VME, or custom parallel buses. Its 200 MHz internal operation allows glue-logic conversion at speeds that match most peripheral buses, while the four embedded array blocks (EABs) provide dual-port RAM for FIFO buffering between asynchronous clock domains. Placing the part between two bus connectors with proper VCCIO 3.3V rail isolation, designers can replace multiple 74-series TTL chips with a single reconfigurable device that adapts to evolving interface standards. The 144-LQFP footprint is the same as classic glue-logic packages, simplifying PCB migration from discrete-logic implementations.
Recommended
Industrial Control Logic Replacement
In factory automation and process control, the EP1K10TC144-3 replaces obsolete discrete-logic boards implementing state controllers, timer chains, and alarm encoders. With 576 logic elements, it can hold tens of state machines plus combinational encoding logic, and its SRAM-based configuration supports field updates via JTAG when product firmware changes. Industrial users benefit from the part's commercial 0-70Β°C rating suitable for enclosed control cabinets and the 144-LQFP package's compatibility with standard reflow profiles. A typical design places the FPGA between sensor-conditioning ASICs and a microcontroller SPI/IΒ²C bus, offloading bit-banging and protocol conversion. Note that for new industrial designs, AEC-Q100 is not applicable; choose a modern industrial-grade Cyclone or MAX 10 instead.
Recommended
Telecom Glue Logic and Protocol Conversion
The EP1K10TC144-3 was widely deployed in early-2000s telecom equipment for low-speed protocol conversion, framing, and clock-domain crossing. Its four embedded array blocks implement dual-port RAM buffers for HDLC, UART, or framing tasks, while the 200 MHz internal frequency supports high-speed serial bit alignment. The 92 I/Os accommodate parallel TDM bus interfaces common in T1/E1 and H.110 telecom backplanes. In a typical application the FPGA sits between a framer IC and a network processor, offloading cell delineation and alarm detection. Designers should validate jitter tolerance with the VCCINT 2.5V supply and observe the Altera recommended PLL configuration guidelines if more than one clock domain is needed.
Recommended
Embedded System Peripheral Expansion
Embedded motherboards in test, medical, and instrumentation equipment frequently pair a low-cost microcontroller with an FPGA that adds custom peripherals: PWM generators, encoder counters, custom LCD controllers, or parallel data acquisition channels. The EP1K10TC144-3 with 10K gates and 92 I/Os is sized for exactly this role, providing several dozen soft peripherals alongside bus-interface glue. The 12 Kbits of block RAM serves as FIFO storage for ADC/DAC streaming. In a typical design, the FPGA connects to the MCU via an 8/16-bit SRAM-style bus, offloading deterministic timing tasks from the MCU's interrupt-driven software. Verify timing margin with Quartus II Static Timing Analysis since the part is in NRND status.
Recommended
Test Equipment Custom Instrumentation
Custom ATE and bench-instrument designers use the EP1K10TC144-3 to implement pattern generators, custom stimulus sequencers, and protocol-aware triggering. The 200 MHz operation supports high-speed digital stimulus generation, and the dual-port EAB RAM stores long test patterns or captured waveforms. The 144-LQFP package allows inspection-friendly hand-soldering for prototype builds, and JTAG-based programming enables rapid firmware iteration during development. A typical test fixture places the FPGA between a USB or Ethernet host controller and a device-under-test, with the FPGA translating high-level commands into device-specific timing sequences. The NRND status means engineers should plan migration to MAX 10 or Cyclone for new ATE platforms.
Recommended
Legacy Design Maintenance and Repair
The EP1K10TC144-3 remains an active maintenance component for installed equipment in telecom central offices, industrial control systems, and military electronics with multi-decade service lives. Repair depots and OEM service organizations use it to rebuild failed boards without redesigning the surrounding PCB. With 144-LQFP same-as-original packaging, the part drops into existing boards designed in the early 2000s. Authorized distributor stock at DigiKey and Heisener (verified 2026-09-07) supports repair operations. For long-term support, customers should engage Intel / Altera franchised distributors about lifetime-buy arrangements or migrate to the Cyclone IV EP4CE6E22, which offers a pin-compatible 144-pin footprint and modern Quartus Prime toolchain.
Recommended
Recommended Products Summary
Engineering reference data for EP1K10TC144-3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1K10TC144-3N | EP1K10TC144-2N | EP1K10TC144-1N | EP1K30TC144-3 |
|---|---|---|---|---|---|
| Package | 144-LQFP (TQFP144) | 144-LQFP (TQFP144) - same | 144-LQFP (TQFP144) - same | 144-LQFP (TQFP144) - same | 144-LQFP (TQFP144) - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Family | ACEX-1K | ACEX-1K | ACEX-1K | ACEX-1K | ACEX-1K |
| Typical Gates | 10,000 | 10,000 | 10,000 | 10,000 | 30,000 |
| Speed Grade | -3 (fastest) | -3 (fastest) | -2 (mid) | -1 (slowest) | -3 (fastest) |
| Logic Elements | 576 | 576 | 576 | 576 | 1,728 |
| Embedded RAM Bits | 12,288 | 12,288 | 12,288 | 12,288 | 24,576 |
| User I/O Pins | 92 | 92 | 92 | 92 | 92 |
| RoHS / Lead-Free | Non-RoHS (SnPb) | RoHS / Lead-Free | RoHS / Lead-Free | RoHS / Lead-Free | Non-RoHS (SnPb) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Highest speed grade in same-footprint ACEX-1K family (vs EP1K10TC144-2N)
- RoHS compliance availability in same package (vs EP1K10TC144-3N)
- Smallest ACEX-1K member (10K gates) with 92 I/Os (vs EP1K30TC144-3)
Design Notes
The EP1K10TC144-3 requires separate 2.5V VCCINT and 3.3V VCCIO rails; place 0.1Β΅F decoupling capacitors adjacent to every VCCINT and VCCIO pin pair, plus a single 10Β΅F bulk tantalum or ceramic capacitor near the package. Power-on sequencing is not critical but VCCINT should reach 2.5V within 100ms of VCCIO reaching 3.3V to avoid latch-up; in-circuit supervisors are recommended for production boards. Estimated: ICCINT typical ~50 mA and ICCIO ~10 mA per bank based on ACEX-1K family characteristics - verify with worst-case design utilization via the Quartus II PowerPlay analyzer.
Route all four VCCIO bank supplies (VCCIO1-VCCIO4) as wide traces or planes with multiple vias to inner planes; the 144-LQFP package's lead pitch is 0.5 mm and requires 4-mil trace/space rules with microvia stack-ups for dense breakout. Place the configuration EEPROM or MCU configuration driver within 50 mm of DCLK/nCONFIG/nSTATUS/CONF_DONE to avoid signal-integrity issues. Keep JTAG TCK trace under 100 mm with 22Ξ© series damping if longer routing is unavoidable. Connect MSEL0/MSEL1 to defined logic levels (typically 0/0 for AS mode or 1/0 for PS mode) - do not leave floating.
ACEX-1K SRAM-based FPGAs lose configuration on power-down - a non-volatile configuration source (EPC1, EPC2, MCU bootloader, or flash) is mandatory. Do not leave JTAG TDI/TMS floating during operation; tie them to known logic levels via 10kΞ© pull-ups. The configuration clock (DCLK) must be stable before nCONFIG is released. Avoid 5V signals on I/O pins without external series resistors, since VCCIO is 3.3V. For multi-clock designs, use the dedicated CLK pins (CLK0-CLK3) rather than routed clocks to minimize skew.
Estimated: at 200 MHz toggle rate with 70% utilization across 576 LEs, the EP1K10TC144-3 dissipates approximately 0.5-0.8W. The 144-LQFP package has a theta_JA of approximately 35-45 C/W on a standard JEDEC 4-layer PCB, resulting in a 20-35 C junction temperature rise above ambient - well within the 0-70 C commercial rating. For higher utilization designs, add thermal vias under the exposed die pad region and route inner copper planes to spread heat. Do not use the part in sealed enclosures above 60 C ambient without verifying junction temperature via the thermal-resistance formula Tj = Ta + (Pd Γ theta_JA).
Compliance Information
EP1K10TC144-3 (SnPb terminal finish) is non-RoHS; choose EP1K10TC144-3N for RoHS/lead-free compliance. ACEX-1K family is not AEC-Q100 qualified (commercial grade only). Reach and conflict-minerals compliance per Intel / Altera product declaration.
