EP1K10TC144-2N - 10K Gate ACEX-1K FPGA, 92 I/O, TQFP-144 | Intel / Altera
MPN: EP1K10TC144-2N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EP1K10TC144-2N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1K10TC144-1N
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View Datasheet βEP1K10TC144-3N
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View Datasheet βEP1K10TC144-1
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View Datasheet βEP1K10TC144-2
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View Datasheet βEP1K10TC144-2N Maximum Ratings & Electrical Characteristics
| Family | ACEX-1K |
| Typical Gates | 10,000 |
| Logic Elements | 576 |
| Embedded RAM Bits | 12,288 |
| Embedded Array Blocks (EABs) | 12 |
| Logic Array Blocks (LABs) | 72 |
| User I/O Pins | 92 |
| Package | TQFP-144 (TC) 22x22 mm, 0.5 mm pitch |
| Speed Grade | -2 |
| Core Voltage | 2.5 V |
| Operating Temperature | 0 C to +70 C (commercial) |
| Configuration Method | Serial / JTAG |
| JTAG Support | IEEE 1149.1 boundary scan |
| Mounting Type | Surface Mount |
EP1K10TC144-2N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 2) |
| Pin 12 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | GND β Ground |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | VCCINT β Core supply voltage (2.5 V) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | I/O β User I/O pin (bank 3) |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | VCCINT β Core supply voltage (2.5 V) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 3) |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | I/O β User I/O pin (bank 3) |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 55 | GND β Ground |
| Pin 56 | I/O β User I/O pin (bank 3) |
| Pin 57 | I/O β User I/O pin (bank 3) |
| Pin 58 | I/O β User I/O pin (bank 4) |
| Pin 59 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | I/O β User I/O pin (bank 4) |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | I/O β User I/O pin (bank 4) |
| Pin 70 | VCCINT β Core supply voltage (2.5 V) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | I/O β User I/O pin (bank 4) |
| Pin 75 | I/O β User I/O pin (bank 4) |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | I/O β User I/O pin (bank 4) |
| Pin 78 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 79 | GND β Ground |
| Pin 80 | I/O β User I/O pin (bank 4) |
| Pin 81 | I/O β User I/O pin (bank 1) |
| Pin 82 | I/O β User I/O pin (bank 1) |
| Pin 83 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 84 | I/O β User I/O pin (bank 1) |
| Pin 85 | I/O β User I/O pin (bank 1) |
| Pin 86 | GND β Ground |
| Pin 87 | I/O β User I/O pin (bank 1) |
| Pin 88 | I/O β User I/O pin (bank 1) |
| Pin 89 | I/O β User I/O pin (bank 1) |
| Pin 90 | I/O β User I/O pin (bank 1) |
| Pin 91 | I/O β User I/O pin (bank 1) |
| Pin 92 | I/O β User I/O pin (bank 1) |
| Pin 93 | I/O β User I/O pin (bank 1) |
| Pin 94 | I/O β User I/O pin (bank 1) |
| Pin 95 | I/O β User I/O pin (bank 1) |
| Pin 96 | I/O β User I/O pin (bank 1) |
| Pin 97 | I/O β User I/O pin (bank 1) |
| Pin 98 | I/O β User I/O pin (bank 1) |
| Pin 99 | I/O β User I/O pin (bank 1) |
| Pin 100 | I/O β User I/O pin (bank 1) |
| Pin 101 | I/O β User I/O pin (bank 1) |
| Pin 102 | I/O β User I/O pin (bank 1) |
| Pin 103 | I/O β User I/O pin (bank 1) |
| Pin 104 | I/O β User I/O pin (bank 1) |
| Pin 105 | I/O β User I/O pin (bank 1) |
| Pin 106 | I/O β User I/O pin (bank 1) |
| Pin 107 | I/O β User I/O pin (bank 1) |
| Pin 108 | I/O β User I/O pin (bank 1) |
| Pin 109 | I/O β User I/O pin (bank 1) |
| Pin 110 | I/O β User I/O pin (bank 1) |
| Pin 111 | I/O β User I/O pin (bank 1) |
| Pin 112 | I/O β User I/O pin (bank 1) |
| Pin 113 | I/O β User I/O pin (bank 1) |
| Pin 114 | I/O β User I/O pin (bank 1) |
| Pin 115 | I/O β User I/O pin (bank 1) |
| Pin 116 | I/O β User I/O pin (bank 1) |
| Pin 117 | I/O β User I/O pin (bank 1) |
| Pin 118 | I/O β User I/O pin (bank 1) |
| Pin 119 | I/O β User I/O pin (bank 1) |
| Pin 120 | I/O β User I/O pin (bank 1) |
| Pin 121 | I/O β User I/O pin (bank 1) |
| Pin 122 | I/O β User I/O pin (bank 1) |
| Pin 123 | I/O β User I/O pin (bank 1) |
| Pin 124 | TDI β JTAG test data input |
| Pin 125 | TMS β JTAG test mode select |
| Pin 126 | TCK β JTAG test clock |
| Pin 127 | TDO β JTAG test data output |
| Pin 128 | nSTATUS β Configuration status (open-drain) |
| Pin 129 | nCONFIG β Configuration control (active-low) |
| Pin 130 | DCLK β Configuration clock input |
| Pin 131 | DATA0 β Configuration data input |
| Pin 132 | CONF_DONE β Configuration complete (open-drain) |
| Pin 133 | MSEL0 β Configuration mode select 0 |
| Pin 134 | MSEL1 β Configuration mode select 1 |
| Pin 135 | I/O β User I/O pin (bank 1) |
| Pin 136 | I/O β User I/O pin (bank 1) |
| Pin 137 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 138 | I/O β User I/O pin (bank 1) |
| Pin 139 | I/O β User I/O pin (bank 1) |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β User I/O pin (bank 1) |
| Pin 142 | I/O β User I/O pin (bank 1) |
| Pin 143 | I/O β User I/O pin (bank 1) |
| Pin 144 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1K10TC144-2N is suitable for 6 applications: Industrial Glue Logic Replacement, Legacy Peripheral Bridging, Low-Density DSP Pre/Post-Processing, Custom State Machine Controllers, Telecom Line Card Glue Logic, Military & Aerospace Legacy Systems.
Industrial Glue Logic Replacement
The EP1K10TC144-2N replaces multiple 74-series TTL and CMOS glue-logic ICs on legacy industrial controllers with a single programmable device, reducing board area and assembly cost. Its 576 logic elements and 12,288 bits of embedded RAM comfortably accommodate typical state machines, address decoders, and timing generators used in PLC backplanes and motor-control boards. The 92 user I/O pins and four independently supplied VCCIO banks allow direct interfacing with 3.3 V and 2.5 V peripherals on the same PCB. Designers benefit from Quartus II synthesis, which preserves schematic capture from MAX+PLUS II designs, easing migration of proven legacy logic.
Recommended
Legacy Peripheral Bridging
The EP1K10TC144-2N acts as a custom bridge between mismatched peripherals such as UART, IΒ²C, SPI, and parallel buses in industrial PCs and test equipment. Each of the 12 embedded array blocks can be configured as dual-port RAM, ROM, or a small multiplier, supporting protocol-conversion FIFOs without external memory. The 2.5 V core and JTAG-based in-system programming enable field updates through the standard IEEE 1149.1 test access port. Designers targeting legacy PC/104 and VMEbus cards can leverage the abundant I/O count and IEEE 1149.1 boundary-scan testability to replace discrete bridge ASICs.
Recommended
Low-Density DSP Pre/Post-Processing
The EP1K10TC144-2N implements small DSP functions such as digital filters, FFT pre-processors, and CRC engines alongside an external DSP or microcontroller in cost-sensitive test and measurement equipment. The 12 embedded array blocks each support dedicated multiplier modes, allowing 8-bit or 12-bit multiply-accumulate (MAC) operations at system clock rates up to 50 MHz. While the 10K-gate density is modest by modern standards, it provides just enough logic for sensor conditioning and signal conditioning pipelines in portable instrumentation. Designers pair the FPGA with an external ADC/DAC for complete analog signal chains.
Recommended
Custom State Machine Controllers
The EP1K10TC144-2N excels as a custom state-machine controller for industrial automation, robotics, and material-handling equipment where deterministic sequencing and reliable I/O control are essential. The 576 logic elements and 72 logic array blocks map cleanly onto multi-state FSMs with parallel datapath logic, while 92 user I/O pins comfortably drive sensor inputs, actuator relays, and HMI display interfaces. JTAG boundary-scan testability simplifies board-level debugging and in-field firmware updates through the standard test access port. Designers value the predictable timing closure achievable with Quartus II timing analysis for safety-critical sequencing.
Recommended
Telecom Line Card Glue Logic
The EP1K10TC144-2N serves as glue logic on telecom line cards, replacing discrete bus-isolation, address-decoding, and interrupt-routing ICs around network processors and framer ASICs. The 12,288 bits of embedded RAM support small lookup tables used for header processing and routing decisions at line-card speeds. Four I/O banks allow direct 3.3 V interfacing to PHY chips and 2.5 V connections to the network processor, eliminating external level shifters. Designers benefit from low-cost legacy parts availability for long-lifecycle telecom infrastructure where reliability trumps performance.
Recommended
Military & Aerospace Legacy Systems
The EP1K10TC144-2N continues to serve in long-lifecycle military, aerospace, and avionics platforms designed around ACEX-1K silicon in the late 1990s. While not radiation-hardened by modern standards, the commercial-grade device is qualified by many programs through up-screening processes and remains in service on legacy avionic displays, flight data recorders, and ground-test equipment. The 144-pin TQFP package is well-suited to high-vibration environments where fine-pitch BGAs are not desirable. Designers performing obsolescence management rely on factory-surplus and authorized-stock distributors for ongoing support.
Recommended
Recommended Products Summary
Engineering reference data for EP1K10TC144-2N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1K10TC144-1N | EP1K10TC144-3N | EP1K10TC144-1 | EP1K10TC144-2 |
|---|---|---|---|---|---|
| Package | TQFP-144 (TC) 22x22 mm | TQFP-144 (TC) - same | TQFP-144 (TC) - same | TQFP-144 (TC) - same | TQFP-144 (TC) - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | ACEX-1K | ACEX-1K | ACEX-1K | ACEX-1K | ACEX-1K |
| Logic Elements | 576 | 576 | 576 | 576 | 576 |
| Embedded RAM (bits) | 12,288 | 12,288 | 12,288 | 12,288 | 12,288 |
| User I/O Pins | 92 | 92 | 92 | 92 | 92 |
| Speed Grade | -2 | -1 (faster) | -3 (slower) | -1 (faster) | -2 (same) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Unit Price (qty 1, USD) | 18.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Balanced speed grade -2 with industry-standard TQFP-144 footprint (vs EP1K10TC144-1N)
- TQFP-144 is hand-solderable and field-rework friendly (vs EP1K10FC256-2N (FBGA-256))
- Mature ACEX-1K architecture with extensive Quartus II legacy support (vs Cyclone EP1C3T144C8N)
- On-site authentication and traceability through authorized distributors (vs Grey-market EP1K10TC144-2N lots)
Design Notes
The EP1K10TC144-2N requires a clean 2.5 V VCCINT rail for the core plus separate VCCIO supplies (2.5 V or 3.3 V) for each of the four I/O banks. Decouple each VCCINT and VCCIO pin with a 0.1 Β΅F X7R ceramic capacitor placed within 5 mm of the package pin, and add a bulk 10 Β΅F tantalum capacitor near the FPGA supply entry point. Avoid routing high-frequency switching signals directly across the VCCINT plane to minimize core supply noise.
The TQFP-144 package has a theta_JA of approximately 35 Β°C/W in still air and around 25 Β°C/W with 400 cmΒ² of 4-layer PCB copper. At typical 200 mA core current (500 mW dissipation), the junction temperature rises only 17 Β°C above ambient, so no heatsink is required. Estimated: assumed 4-layer JEDEC-standard test board and natural convection. Designers targeting sealed enclosures should add thermal vias beneath the package to the internal ground plane.
TQFP-144 with 0.5 mm pitch demands strict PCB layout discipline: trace width 0.15 mm minimum, via 0.3 mm drill, and a continuous ground plane beneath the package. Route all 92 user I/O signals on outer layers only and avoid stubs longer than 5 mm. Keep JTAG signals (TDI/TMS/TCK/TDO) bundled together and isolated from high-speed switching I/O. Solder paste stencil aperture should be 1:1 to land pad with 0.1 mm relief for fine-pitch 0.5 mm QFP packages.
Do not apply 5 V signals directly to the EP1K10TC144-2N user I/O pins because the device lacks 5 V-tolerant inputs; damage will result. Use external resistor dividers or level shifters (such as 74LVC245) for any 5 V source. Also ensure the nCONFIG and MSEL pins are correctly strapped for the desired configuration mode (e.g., MSEL=00 for passive serial). Configuration failures are most often caused by incorrect MSEL settings rather than silicon defects.
Series-terminate high-speed outputs (above 33 MHz) with a 33 Ξ© resistor placed within 5 mm of the FPGA driver pin to dampen reflections on 50 Ξ© controlled-impedance traces. For LVTTL outputs driving long capacitive loads, slew-rate adjustment via Quartus II settings reduces EMI. The four I/O banks must each have its VCCIO plane decoupled locally; mixing VCCIO voltages on a single bank is not supported and causes latch-up risk.
Compliance Information
RoHS status is not stated in the verified web data; the ACEX-1K family predates widespread RoHS adoption. Mark compliance fields as 'unknown' until factory documentation can be reviewed.
