EP20K100CB356C7ES - APEX20K 100K Gate FPGA | Intel | 356-BGA
MPN: EP20K100CB356C7ES β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132 | $1,320.00 |
| 100 | $118 | $11,800.00 |
| 500 | $105 | $52,500.00 |
| 1,000 | $92 | $92,000.00 |
Drop-in alternatives for EP20K100CB356C7ES β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP20K100CB356C7
β Drop-Inβ In Stock
$71 / Unit
View Datasheet βEP20K100BC356-1
β Drop-Inβ In Stock
$92.75 / Unit
View Datasheet βEP20K200CB356C7
β Drop-Inπ Reference alternative (not in catalog)
EP20K100CB356C8
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$82 / Unit
View Datasheet βEP20K100CB356C9
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
Contact for price
View Datasheet βEP20K100CB356C7ES Maximum Ratings & Electrical Characteristics
| Family | APEX20K |
| Logic Elements | 4,160 |
| Typical Gates | 100,000 |
| Maximum System Gates | 263,000 |
| Embedded Memory (RAM bits) | 53,248 |
| User I/O Pins | 252 |
| Package | 356-BGA |
| Speed Grade | C7 |
| Core Voltage | 1.8 V |
| I/O Voltage Compatibility | 2.5 V / 3.3 V |
| Configuration Method | JTAG / Passive Serial |
| Process Technology | SRAM-based CMOS |
| Mounting Type | Surface Mount (BGA) |
EP20K100CB356C7ES Pin Configuration
| Pin A1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A2 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A3 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A4 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A5 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A6 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A7 | VCCINT β Core supply 1.8 V |
| Pin A8 | GND β Ground |
| Pin A9 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A10 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A11 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A12 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A13 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A14 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A15 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A16 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin A17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin B1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin B2 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin B17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin C1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin C17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin D1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin D17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin E1 | TCK β JTAG Test Clock |
| Pin E17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin F1 | TMS β JTAG Test Mode Select |
| Pin F17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin G1 | TDI β JTAG Test Data In |
| Pin G17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin H1 | TDO β JTAG Test Data Out |
| Pin H17 | VCCIO β I/O supply 3.3 V / 2.5 V |
| Pin J1 | nCONFIG β Configuration control (active low) |
| Pin J17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin K1 | CONF_DONE β Configuration done status |
| Pin K17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin L1 | nSTATUS β Configuration status (active low) |
| Pin L17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin M1 | DCLK β Configuration clock |
| Pin M17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin N1 | DATA0 β Configuration data input |
| Pin N17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin P1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin P17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin R1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin R17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin T1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin T17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin U1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin U17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin V1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin V17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin W1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin W17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin Y1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin Y17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin AA1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin AA17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin AB1 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin AB17 | I/O β User I/O bank reference (per BGA ball-map) |
| Pin AC1 | I/O β User I/O ball reference (per BGA ball-map) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP20K100CB356C7ES is suitable for 7 applications: Telecommunications Switching Equipment, Video Broadcast and Image Processing, Industrial Motor Control, DSP Co-Processing in Medical Imaging, Broadband Access Equipment, Multi-Channel Data Acquisition Systems, Legacy Embedded Computing Platforms.
Telecommunications Switching Equipment
The EP20K100CB356C7ES's 4,160 logic elements and 252 user I/O pins make it well suited for telecom line-card and switch-fabric designs. Its SRAM-based fabric enables rapid protocol updates for TDM-to-Ethernet bridging or ATM cell processing. The APEX20K family's 53,248 bits of embedded memory serve as on-chip cell buffers, reducing external SRAM requirements. Operating at C7 speed grade, the device meets typical 100 MHz telecom datapath timing. The 356-BGA package provides the high I/O count needed for parallel bus interfaces to TDM framers and PHY devices.
Recommended
Video Broadcast and Image Processing
The EP20K100CB356C7ES handles real-time video processing tasks such as SDI/HDMI bridging, color-space conversion, and image filtering. Its 4-input LUT architecture and embedded array blocks (EABs) implement multipliers and line buffers efficiently, while 252 I/O pins accommodate parallel video buses. The C7 speed grade supports typical pixel-clock rates up to 100 MHz, suitable for standard-definition and entry-level HD processing. The device's reprogrammability enables late-stage algorithm changes, valuable for evolving broadcast standards.
Recommended
Industrial Motor Control
In industrial motor-drive systems, the EP20K100CB356C7ES implements field-oriented control (FOC), space-vector PWM, and encoder feedback processing. Its 252 I/O pins connect to multiple ADC channels for current sensing and to gate-driver ICs for inverter control. The SRAM-based fabric allows tuning of control loops per motor variant without hardware changes. The C7 speed grade supports PWM frequencies above 20 kHz, sufficient for silent-drive operation. The 356-BGA package supports surface-mount assembly on industrial controller PCBs.
Recommended
DSP Co-Processing in Medical Imaging
The EP20K100CB356C7ES serves as a co-processor to a host CPU or DSP in ultrasound and MRI front-end systems, accelerating FFT and convolution operations. Its embedded array blocks implement 18x18 multipliers critical for FIR filters, while the 53,248-bit embedded memory holds coefficient tables. With 4,160 logic elements, the device can run parallel multiplier-accumulator pipelines. The 356-BGA package supports the high I/O count needed for parallel data paths from analog front-end ADCs.
Recommended
Broadband Access Equipment
In DSLAMs, CMTS, and PON optical line terminals, the EP20K100CB356C7ES handles packet classification, queue management, and traffic shaping. Its 252 I/O pins interface with network processors and SerDes devices, while the reprogrammable logic adapts to evolving QoS algorithms. The C7 speed grade supports typical 100 MHz system bus operation. The APEX20K's SRAM-based configuration enables field upgrades as broadband standards evolve.
Recommended
Multi-Channel Data Acquisition Systems
The EP20K100CB356C7ES suits multi-channel data-acquisition systems in test and measurement, implementing timing generators, channel synchronizers, and on-the-fly DSP. Its 252 I/O pins accommodate 16+ parallel ADC/DAC channels plus digital trigger lines, while the 4,160 logic elements run FIR filters per channel. The C7 speed grade supports per-channel sample rates up to 100 MSPS in pipelined designs. The 356-BGA package fits standard 6-layer data-acquisition PCBs.
Recommended
Legacy Embedded Computing Platforms
The EP20K100CB356C7ES supports existing embedded computing platforms - avionics, defense, and industrial controllers - that were designed around the APEX20K family. Maintaining these systems requires the same footprint part; the EP20K100CB356C7ES provides bitstream-compatible replacement for in-service boards. Its 1.8 V core and 3.3 V I/O compatibility match existing power architectures. The 356-BGA footprint preserves the original PCB layout, avoiding costly board respins.
Recommended
Recommended Products Summary
Engineering reference data for EP20K100CB356C7ES β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K100CB356C7 | EP20K100BC356-1 | EP20K200CB356C7 | EP20K100CB356C8 | EP20K100CB356C9 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 356-BGA | 356-BGA - same | 356-BGA - same | 356-BGA - same | 356-BGA - same | 356-BGA - same |
| Logic Elements | 4,160 | 4,160 | 4,160 | 8,320 | 4,160 | 4,160 |
| Typical Gates | 100,000 | 100,000 | 100,000 | 200,000 | 100,000 | 100,000 |
| Maximum System Gates | 263,000 | 263,000 | 263,000 | 526,000 | 263,000 | 263,000 |
| Speed Grade | C7 | C7 | -1 (industrial) | C7 | C8 (slower) | C9 (slowest) |
| Embedded Memory (RAM bits) | 53,248 | 53,248 | 53,248 | 106,496 | 53,248 | 53,248 |
| User I/O Pins | 252 | 252 | 252 | 252 | 252 | 252 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
Key Differentiators
- Embedded System (ES) variant with verified firmware/configuration support (vs EP20K100CB356C7)
- Higher logic density option in same package footprint (vs EP20K200CB356C7)
- Industrial temperature grade variant in same package (vs EP20K100BC356-1)
Design Notes
Power sequencing is critical for the APEX20K family. The 1.8 V VCCINT core supply must ramp before the VCCIO I/O supply to prevent latch-up. Use a power-management IC with PG (power-good) signal feedback or a discrete MOSFET arrangement to enforce sequencing. Typical inrush current for the 356-BGA package is 1.5-2 A on VCCINT; bulk decoupling requires at least 4x 22 uF tantalum capacitors plus 0.1 uF ceramics per quadrant of the BGA.
Estimated: based on a typical APEX20K design with 60% logic utilization and 100 MHz toggle rate, the 356-BGA package dissipates approximately 1.5-2.0 W. Use a 6-layer PCB with dedicated ground and power planes, and stitch the BGA thermal balls (typically the central array) to the inner ground plane with 0.3 mm thermal vias. At higher utilization (>80%) or ambient temperatures above 70 C, attach a small heatsink or use forced-air cooling to keep junction temperature below 125 C.
BGA assembly for the 356-ball package requires 0.8 mm or 1.0 mm pitch with NSMD (non-solder-mask-defined) pads for reliable solder joint formation. Use ENIG (Electroless Nickel Immersion Gold) surface finish and a 245 C peak reflow profile per JEDEC J-STD-020. Plan escape routing in the top layer with 0.1 mm trace/space for the inner balls; outer rows can route on two layers using micro-via technology. X-ray inspection after reflow is mandatory because BGA joints are hidden under the package.
Do not assume a 3.3 V-only supply is sufficient - the APEX20K requires 1.8 V VCCINT regardless of I/O voltage. Do not forget the MSEL (mode-select) pin settings; wrong configuration mode results in configuration failure and a held nSTATUS low. For passive-serial configuration, ensure the EPC2 or EPC16 configuration PROM is programmed with the correct bitstream and that the DCLK frequency does not exceed 100 MHz. Finally, account for configuration time (~50 ms typical) in system boot sequencing.
Compliance Information
Compliance information for the obsolete EP20K100CB356C7ES was not present in the verified web data; values set to 'unknown' per data authenticity rules. RoHS/REACH compliance for APEX20K-era devices was typically 'not compliant' or 'transition-only', but verify with manufacturer documentation before new production orders.
