EPM9560RC304-3 - MAX 9000 EPLD, 560 Macro Cells, 304-pin RQFP | Intel
MPN: EPM9560RC304-3 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.1 | $2,710.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $18.9 | $18,900.00 |
Drop-in alternatives for EPM9560RC304-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560RC304-2N
✅ Drop-In✓ In Stock
$149 / Unit
View Datasheet →EPM9560RC304-20C
✅ Drop-In✓ In Stock
$162 / Unit
View Datasheet →EPM9560RC304-15N
✅ Drop-In✓ In Stock
$19.8 / Unit
View Datasheet →EPM9560RC304-10
✅ Drop-In✓ In Stock
$17.6 / Unit
View Datasheet →EPM9560RC-304
✅ Drop-In✓ In Stock
$62 / Unit
View Datasheet →EPM9560RC304-3 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 (EPLD) |
| Usable Gates | 12,000 |
| Macro Cells | 560 |
| Maximum Operating Frequency | 95 MHz (speed grade -3) |
| Supply Voltage (VCCINT) | 5 V |
| Technology | UV-erasable CMOS EPROM |
| Package | 304-pin RQFP (Plastic Quad Flat Pack) |
| Programming Interface | JTAG / 4-wire ISP (ByteBlaster compatible) |
| Operating Temperature | 0C to +70C (commercial) |
| Mounting Type | Surface Mount |
| Speed Grade | -3 (fastest) |
EPM9560RC304-3 304-pin rqfp (plastic quad flat pack) Pin Configuration Guide
Complete pinout information for EPM9560RC304-3 (304-pin rqfp (plastic quad flat pack) package) with [DATA_NEEDED: user I/O count] pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC304-3.
Refer to the datasheet for full pin configuration.
Estimated pin count: [DATA_NEEDED: user I/O count] pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC304-3 is suitable for 6 applications: 5 V Telecom Bus Controller, Industrial PLC Glue Logic, Legacy Microprocessor Peripheral Adapter, Peripheral Interface State Machine, Avionics / Defense Legacy Replacement, Test & Measurement Instrument Front-End.
5 V Telecom Bus Controller
The EPM9560RC304-3 fits 5 V telecom bus controller designs because of its native 5 V VCCINT (no level shifting needed for legacy TTL/CMOS peripherals) and 560 macro cells - enough to encode multi-master arbitration, address decoding, and interrupt steering on a single device. With -3 speed grade ~95 MHz fMAX and deterministic PIA routing, the device reliably meets the timing budgets of classic PCI, VME, and proprietary telecom backplanes. Its 304-pin RQFP exposes a wide I/O count suitable for parallel bus interfacing. Designers pair it with a small Altera configuration EEPROM or JTAG ByteBlaster for in-system programming.
Recommended
Industrial PLC Glue Logic
The EPM9560RC304-3 is well suited as glue logic in industrial PLC chassis where it consolidates discrete 74-series logic, address decoding, and timing generators into one 304-pin RQFP device. Its 12,000 usable gates and 560 macro cells cover typical PLC peripheral multiplexing, encoder/counter interfacing, and isolated communication front-ends. The 5 V core integrates directly with 5 V PLC backplane logic and opto-isolated I/O. The -3 speed grade provides comfortable timing headroom for encoder sampling at moderate kHz-to-MHz rates, while pin-compatible slower grades (-10, -15, -20) offer cost-down options once timing is closed.
Recommended
Legacy Microprocessor Peripheral Adapter
The EPM9560RC304-3 is ideal as a peripheral adapter for legacy 5 V microprocessors such as the 8051 family, 68k, or x86 embedded controllers. It absorbs chip-select decoding, wait-state generation, and bus-cycle translation using its 560 macro cells, offloading the CPU from real-time glue tasks. The 304-pin RQFP exposes enough user I/O for multiple 8/16-bit peripheral buses in parallel. The -3 speed grade sustains deterministic bus-to-peripheral timing, and the JTAG ISP interface allows field firmware updates without removing the device from the board.
Recommended
Peripheral Interface State Machine
The EPM9560RC304-3 implements complex state machines for serial/parallel peripheral interfaces (UART, SPI, I2C bridges, parallel ATA, custom protocols) within its 560 macro cells. The deterministic PIA routing ensures predictable state-machine propagation delays - critical when handshake timing drives protocol compliance. Its 304-pin RQFP package supports multi-channel designs where each channel maps to dedicated I/O banks. The -3 speed grade's ~95 MHz fMAX comfortably handles multi-megabaud serial bridging, and the JTAG 4-wire ISP interface accelerates bring-up iterations.
Recommended
Avionics / Defense Legacy Replacement
The EPM9560RC304-3 serves in legacy avionics and defense systems where form-fit-function replacement of older MAX 9000 designs is required and the 5 V core matches existing power rails. Its 560 macro cells and 12,000 usable gates cover mission-computer interface logic, MIL-STD-1553 bridging glue, and redundant bus arbiters. The -3 speed grade provides conservative timing margin for safety-critical applications. The 304-pin RQFP allows direct PCB drop-in replacement of older speed grades; sourcing is constrained to obsolete-market independent distributors and traceable-lot brokers.
Recommended
Test & Measurement Instrument Front-End
The EPM9560RC304-3 functions as a reconfigurable front-end controller in bench and ATE instruments - routing stimulus/response channels, decoding parallel data buses from DUTs, and sequencing handshake protocols. Its 560 macro cells provide enough headroom for multi-channel mux/demux trees and protocol bridges. The -3 speed grade's ~95 MHz fMAX accommodates typical instrumentation data rates up to tens of MHz without timing closure issues. The 304-pin RQFP package supplies abundant I/O for multi-channel instruments, and the JTAG ISP enables rapid lab firmware revisions.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC304-3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-2N | EPM9560RC304-20C | EPM9560RC304-15N | EPM9560RC304-10 | EPM9560RC-304 |
|---|---|---|---|---|---|---|
| Package | 304-pin RQFP | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Macro Cells | 560 | 560 | 560 | 560 | 560 | 560 |
| Speed Grade | -3 (fastest) | -2N (faster) | -20C (slowest commercial) | -15N | -10 | blank (default) |
| Max Internal Frequency (fMAX) | ~95 MHz | >=95 MHz (faster) | ~50 MHz | ~67 MHz | ~75 MHz | [DATA_NEEDED] |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Programming Interface | JTAG / 4-wire ISP | JTAG / 4-wire ISP | JTAG / 4-wire ISP | JTAG / 4-wire ISP | JTAG / 4-wire ISP | JTAG / 4-wire ISP |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest speed grade in the MAX 9560 family (vs EPM9560RC304-20C)
- Maximum timing margin for high-speed 5 V designs (vs EPM9560RC304-15N)
- Pin-to-pin upgrade path for legacy -10 or -15 designs (vs EPM9560RC304-10)
Design Notes
The EPM9560RC304-3 requires a clean 5 V VCCINT rail; place a 0.1 uF ceramic decoupling capacitor adjacent to every VCC/GND pair plus a 10 uF bulk tantalum near the package. The 304-pin RQFP draws dynamic current during JTAG programming and high-utilization logic operation, so add 1-2 additional 1 uF ceramics between VCC and GND planes. Estimated: at 100% toggle rate across all 560 macro cells, ICC can exceed 200 mA - budget power supply accordingly.
The 304-pin RQFP (0.5 mm pitch, ~4-5 cm body) demands a multi-layer PCB with continuous power and ground planes under the device for both decoupling and thermal dissipation. Use 4+ layer stack-up; route all JTAG signals (TDI, TDO, TMS, TCK) as short traces with series 33 ohm termination if cable length exceeds 50 mm. Place the JTAG header within 100 mm to avoid signal-integrity issues during in-system programming.
Do not assume any MAX 9560 speed grade is hot-swappable without revalidating timing closure - while pinout is identical across speed grades, fMAX differs from ~95 MHz (-3) down to ~50 MHz (-20C). A design that meets timing at -3 may fail at -20C; always run a worst-case static timing analysis in MAX+PLUS II or Quartus before committing to a lower-cost grade. Also note: the device is UV-erasable - if your design uses a windowed package variant, plan for erasure time (~30 min UV exposure).
The 304-pin RQFP's ~5 cm package perimeter creates significant lead inductance; for high-speed outputs (>50 MHz) add 22-33 ohm series damping resistors at the driver macro cell pins to control edge rate and reduce ground-bounce noise. Keep critical clock and JTAG TCK traces short and away from high-toggle-rate I/O. Place a ground guard ring around the device on the outer PCB layer to reduce EMI.
Compliance Information
Compliance status not provided in Verified Web Data. MAX 9000 family predates widespread RoHS transition; many lot codes may be non-RoHS - verify lot-specific certification from the distributor before use in RoHS-required assemblies.
