EPM9560RI304-20C - 560-Macrocell MAX 9000 CPLD, 5V, 304-Pin RQFP | Altera
MPN: EPM9560RI304-20C β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.75 | $257.50 |
| 100 | $22.4 | $2,240.00 |
| 500 | $19.85 | $9,925.00 |
| 1,000 | $17.2 | $17,200.00 |
Drop-in alternatives for EPM9560RI304-20C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC304-20C
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$162 / Unit
View Datasheet βEPM9560RI304-20
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View Datasheet βEPM9560RC304-20N
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View Datasheet βEPM9560RC304-20
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View Datasheet βEPM9560RC304-15N
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$19.8 / Unit
View Datasheet βEPM9560RI304-20C Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 |
| Propagation Delay (tpd) | 23.6 ns (speed grade -20) |
| Maximum Internal Frequency | 100 MHz |
| Supply Voltage | 5.0 V |
| Programmability | EEPROM, in-system programmable via JTAG (IEEE 1149.1) |
| Process Technology | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX), third generation |
| Package | 304-pin RQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Operating Temperature (commercial) | 0C to +70C |
EPM9560RI304-20C Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | GND β Ground |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | VCC β 5.0 V supply |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | GND β Ground |
| Pin 13 | TDI β JTAG Test Data In |
| Pin 14 | TMS β JTAG Test Mode Select |
| Pin 15 | TCK β JTAG Test Clock |
| Pin 16 | TDO β JTAG Test Data Out |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | VCC β 5.0 V supply |
| Pin 20 | I/O β User I/O pin (bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI304-20C is suitable for 6 applications: Industrial Control Glue Logic, Telecommunications Bus Interface, ASIC Prototyping, Legacy 5V System Glue Logic Replacement, Peripheral Controller for Printers and Storage, Address Decoder and Bus Arbiter.
Industrial Control Glue Logic
The EPM9560RI304-20C is widely used as glue logic in industrial controllers because of its 212 user I/O pins and deterministic 23.6 ns pin-to-pin delay, which lets a single device replace multiple 74LS/74HC discrete logic ICs. Its 5.0 V tolerance and 0C to +70C commercial operating range fit factory-floor backplanes and PLC I/O cards that still rely on 5V logic. The in-system programmable JTAG interface (IEEE 1149.1) lets field engineers update state-machine firmware without removing the board. With 560 macrocells and 16 LABs, the device can absorb entire bus-state decoders and interrupt-arbiter trees in one chip, reducing BOM count and improving long-term reliability.
Recommended
Telecommunications Bus Interface
The EPM9560RI304-20C suits legacy telecom backplane designs because of its 560 macrocells and 212 I/O pins, which can implement full bus-interface logic for parallel TDM or proprietary data buses. Its 5V I/O directly drives TTL-level telecom backplanes without level shifters, and the JTAG (IEEE 1149.1) ISP interface simplifies board-level test and field updates. With 23.6 ns propagation delay and 100 MHz internal frequency, it can handle address decoding, bus arbitration, and timing-and-control functions for medium-speed telecom peripherals. The 304-pin RQFP package supplies the I/O density required for multi-bus bridges.
Recommended
ASIC Prototyping
The EPM9560RI304-20C is used for ASIC prototyping because it offers 12,000 usable gates and 560 macrocells, enough to emulate mid-complexity custom ASICs at 5V before committing to a foundry run. Its EEPROM non-volatile configuration means prototypes survive power cycling with no boot memory, which matches real ASIC behavior more closely than SRAM-based FPGAs. With deterministic 23.6 ns propagation delay and 100 MHz internal clock, engineers can validate timing-sensitive control logic. The JTAG ISP chain supports fast design-turn loops during early silicon bring-up.
Recommended
Legacy 5V System Glue Logic Replacement
The EPM9560RI304-20C is ideal for sustaining legacy 5V systems where 3.3V-only CPLDs cannot be used. Its 5.0 V VCC tolerance directly interfaces with legacy TTL peripherals, memory, and bus transceivers without external level shifting. With 560 macrocells, the device can absorb whole sections of discrete 74-series logic, reducing board area and improving serviceability through JTAG-driven in-system updates. The 23.6 ns propagation delay and 100 MHz internal frequency cover most glue-logic timing budgets, and the 304-pin RQFP provides 212 I/Os for wide parallel interfaces in legacy backplanes.
Recommended
Peripheral Controller for Printers and Storage
The EPM9560RI304-20C is deployed as a peripheral controller in legacy printers and storage subsystems because its 212 I/O pins and 560 macrocells can drive parallel ATA/IDE buses, stepper-motor control logic, and encoder interfaces simultaneously. Its deterministic 23.6 ns tpd ensures glitch-free state-machine transitions needed for motor commutation, while its 5V tolerance matches the legacy driver stage. JTAG ISP allows firmware updates across long product lifecycles. The 100 MHz internal frequency supports high-rate DMA-style peripheral transfers without external logic.
Recommended
Address Decoder and Bus Arbiter
The EPM9560RI304-20C excels as a central address decoder and bus arbiter in multi-master 5V systems. Its 23.6 ns pin-to-pin propagation delay is fast enough to qualify as a 1-cycle wait-state decoder on most 25-33 MHz 5V microprocessors and DSPs, and 212 I/Os cover wide address and chip-select fanouts. With 16 LABs, complex priority encoders and round-robin arbiters fit comfortably. The EEPROM non-volatile configuration means no boot sequence is needed at power-up, which is critical for deterministic bus responses in industrial- and defense-grade 5V systems.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI304-20C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-20C | EPM9560RI304-20 | EPM9560RC304-20N | EPM9560RC304-20 | EPM9560RC304-15N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 304-pin RQFP | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Propagation Delay (tpd) | 23.6 ns | 23.6 ns | 23.6 ns | 23.6 ns | 23.6 ns | 15 ns (faster, -33%) |
| Max User I/O | 212 | 212 | 212 | 212 | 212 | 212 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Temperature Grade (suffix) | C (commercial 0C to +70C) | C (commercial) | [DATA_NEEDED] | N (industrial) | [DATA_NEEDED] | N (industrial) |
| Programming Interface | JTAG IEEE 1149.1 (ISP) | JTAG IEEE 1149.1 (ISP) | JTAG IEEE 1149.1 (ISP) | JTAG IEEE 1149.1 (ISP) | JTAG IEEE 1149.1 (ISP) | JTAG IEEE 1149.1 (ISP) |
Key Differentiators
- Commercial temperature grade clearly specified (vs EPM9560RI304-20)
- Faster speed grade available on same footprint (vs EPM9560RC304-15N)
- Industrial temperature option on same footprint (vs EPM9560RC304-20N)
Design Notes
The EPM9560RI304-20C is a 5V-only part - applying 3.3V signals to its I/O without proper level translation can damage inputs or cause logic-high misreads. Confirm all driving logic is true 5V TTL-compatible. Unused I/O pins must be left floating or tied to GND through a resistor as specified in the MAX 9000 datasheet to minimize inrush during ISP programming. Decoupling: place 0.1uF ceramic bypass caps close to every VCC/GND pair on the 304-pin RQFP, plus a 10uF bulk tantalum near the device.
JTAG chain integrity is critical for ISP. Keep TCK trace length-matched and short (<2 inches if possible), with a 10k pull-up on TMS and TDI. Add series termination (33 ohm) on TCK if the chain exceeds 4 inches. For multi-device JTAG chains, place the EPM9560RI304-20C so that TDO feeds TDI of the next device without stubs. Maintain solid ground plane under the 304-pin RQFP to reduce switching noise coupling into analog sections of the board.
Estimated: at 100 MHz internal frequency, the EPM9560RI304-20C core draws up to ~250 mA from 5V VCC, so design the 5V regulator for at least 1.5x headroom (~400 mA). Use a low-impedance 5V plane rather than a trace, and add a 10uF tantalum plus 0.1uF ceramic at each VCC pin. During ISP programming, inrush current can spike - ensure bulk capacitance is adequate to hold VCC above 4.75V (the minimum operating voltage).
The 304-pin RQFP package has a theta_JA around 35-40 C/W. In a well-ventilated industrial enclosure at 70C ambient, the junction stays below 100C for typical toggle rates. In sealed or stacked assemblies, derate the toggle rate or add forced-air cooling. For long-life designs, keep junction temperature below 100C to maximize EEPROM write-cycle endurance and device MTBF.
Compliance Information
EPM9560RI304-20C predates modern RoHS documentation requirements. RoHS/REACH/lead-free status is not in the verified web data and is marked [DATA_NEEDED]. The part is commercial-grade (not AEC-Q100).
