EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
MPN: EPM9560RC304-15C ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $38.5 | $385.00 |
| 100 | $32 | $3,200.00 |
| 500 | $27.75 | $13,875.00 |
| 1,000 | $24.5 | $24,500.00 |
Drop-in alternatives for EPM9560RC304-15C — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560RC304-15
✅ Drop-In✓ In Stock
$9.4 / Unit
View Datasheet →EPM9560RC304-10
✅ Drop-In✓ In Stock
$17.6 / Unit
View Datasheet →EPM9560RC304-20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPM9560RC-304
✅ Drop-In✓ In Stock
$62 / Unit
View Datasheet →EPM9560RC304-15C Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation |
| Usable Gates | 12,000 |
| Macro Cells | 560 |
| Logic Array Blocks (LABs) | 16 |
| User I/O Pins (maximum) | 212 |
| Maximum Operating Frequency | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns |
| Supply Voltage | 5.0 V |
| Process Technology | CMOS EEPROM |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Program/Erase Endurance | 100 cycles minimum |
| Package | 304-pin RQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +70 C (Commercial) |
EPM9560RC304-15C 304-pin rqfp Pin Configuration Guide
Complete pinout information for EPM9560RC304-15C (304-pin rqfp package) with 212 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC304-15C.
Refer to the datasheet for full pin configuration.
Estimated pin count: 212 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC304-15C is suitable for 6 applications: High-Density Bus Interface Bridge, Industrial Control State Machine, Telecom Backplane Glue Logic Aggregator, Legacy Peripheral Controller, Pin-Compatible Replacement for EOL 304-pin RQFP CPLDs, Test and Measurement Instrumentation.
High-Density Bus Interface Bridge
The EPM9560RC304-15C's 560 macro cells and 212 user I/O pins make it a strong fit for bridging legacy 5 V parallel buses (e.g. ISA, VME, PC/104) to modern peripheral controllers in industrial backplanes. Its 117.6 MHz fMAX and 15 ns tPD allow pipelined state machines to convert protocols in real time, while the 5 V tolerant I/O interfaces directly to TTL peripherals without level shifters. Engineers typically place the device between the legacy bus connector and an FPGA or SoC, with the JTAG ISP interface used for field-updatable protocol tables. Compared to a discrete 74LS series implementation, a single EPM9560RC304-15C can replace 20-30 discrete logic packages.
Recommended
Industrial Control State Machine
With deterministic pin-to-pin propagation delay and EEPROM non-volatile storage, the EPM9560RC304-15C is ideal for safety-critical industrial state machines such as PLC sequencers, motor-control gating logic, and conveyor controllers. Its 16 Logic Array Blocks each provide 40 macro cells, sufficient for parallel FSM encoding with hot-one or Gray-code safety. The 5 V supply matches the standard industrial 24 V->5 V backplane rail, and the 0 C to +70 C commercial temperature range covers most factory-floor enclosures. Engineers should add 0.1 uF + 10 uF decoupling per VCC pin and a 4.7 kohm pull-up on each JTAG signal to ensure stable ISP in noisy environments.
Recommended
Telecom Backplane Glue Logic Aggregator
The EPM9560RC304-15C can aggregate multiple low-density glue-logic functions (chip-select decoding, wait-state insertion, interrupt steering, FIFO flag combining) into a single programmable device on a telecom backplane. Its 212 user I/O handle the wide busses typical of T1/E1 and SDH framer boards, while the 117.6 MHz fMAX comfortably exceeds the 77 MHz STS-1 rate. The 5 V I/O matches legacy telecom ASIC interfaces, and the JTAG ISP allows in-field reprogramming of switching matrices when carriers reconfigure service tables.
Recommended
Legacy Peripheral Controller
When modern microcontrollers lack enough parallel I/O for legacy peripherals (parallel LCDs, keypads, floppy-disk controllers, IDE interfaces), the EPM9560RC304-15C serves as an external I/O expander and bus controller. Its programmable I/O cells can implement open-drain or 3-state outputs, and per-pin slew-rate control reduces EMI on long cables. The 15 ns tPD enables direct connection to standard 16-bit memory buses at up to ~33 MHz. Engineers use the JTAG port to update peripheral personality on-the-fly, supporting multiple product variants from one PCB.
Recommended
Pin-Compatible Replacement for EOL 304-pin RQFP CPLDs
The EPM9560RC304-15C's 304-pin RQFP footprint makes it a drop-in replacement for other obsolete MAX 9000 family members on the same pinout, extending the lifecycle of legacy boards without PCB rework. Designers typically de-solder the old CPLD and re-solder the EPM9560RC304-15C, then re-program the JTAG image using the original design's configuration data. This is especially valuable in long-lifecycle markets such as aerospace, military, and medical where full board re-spins are cost-prohibitive. The MAX 9000 family shares JTAG programming protocols across all package variants.
Recommended
Test and Measurement Instrumentation
The deterministic timing of the EPM9560RC304-15C makes it suitable for test-and-measurement front-ends where repeatable signal generation and protocol decoding are required. Its 560 macro cells can implement multi-channel pattern generators, programmable counters, or arbitrary waveform sequencers in a single device. The 117.6 MHz fMAX supports serial protocol decode (SPI, I2C, UART) at standard rates, and the JTAG ISP allows lab firmware updates without opening the instrument chassis. The commercial 0-70 C range covers most indoor benchtop and rackmount environments.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC304-15C — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-15 | EPM9560RC304-10 | EPM9560RC304-20 | EPM9560RC-304 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 304-pin RQFP | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Macro Cells | 560 | 560 | 560 | 560 | 560 |
| Speed Grade (tPD) | 15 ns | 15 ns | 10 ns (faster) | 20 ns (slower) | 15 ns equivalent |
| Maximum fMAX | 117.6 MHz | 117.6 MHz | 147 MHz (faster) | 100 MHz (slower) | 117.6 MHz equivalent |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | [DATA_NEEDED] |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| User I/O Pins | 212 | 212 | 212 | 212 | 212 |
Key Differentiators
- Faster 117.6 MHz fMAX in commercial temperature grade (vs EPM9560RC304-20)
- Commercial temperature grade optimized for cost-sensitive designs (vs EPM9560RC304-15)
- 304-pin RQFP footprint maximizes user I/O (vs EPM9560RC208 series)
Design Notes
Estimated: The EPM9560RC304-15C draws up to 300 mA from a single 5.0 V supply at full toggle activity across all 560 macro cells and 212 user I/O. Place a 10 uF bulk tantalum or ceramic capacitor within 1 cm of the device VCC pins, plus a 0.1 uF ceramic decoupling cap adjacent to each VCC/GND pair. During JTAG ISP programming, hold the 5.0 V rail within +/-5% to prevent program-verify failures.
The 304-pin RQFP package has 0.5 mm lead pitch and a 34 mm x 34 mm body. Use a 4-layer PCB with continuous power and ground planes under the device to provide low-impedance return paths. Route all JTAG signals (TDI, TDO, TMS, TCK) with 50 ohm controlled impedance and add 4.7 kohm pull-ups on TMS and TCK. Keep JTAG traces shorter than 150 mm to avoid signal-integrity issues during ISP.
Do not confuse the -15C speed/temperature suffix with the -15 speed grade only - the trailing C denotes Commercial temperature (0 to +70 C). For industrial applications, use the EPM9560RC304-15 variant instead. Also avoid applying JTAG programming voltages other than 5.0 V; the MAX 9000 family does not support 3.3 V ISP and may damage the EEPROM cells if over-driven.
Compliance Information
Compliance data not explicitly listed in the verified web sources for this obsolete part. Confirm RoHS/lead-free status with the distributor before use in regulated markets.
