EPM9560RI304-20 - 560 Macrocell MAX 9000 CPLD, 20ns, RQFP-304 | Intel
MPN: EPM9560RI304-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32 | $320.00 |
| 100 | $26.5 | $2,650.00 |
| 500 | $21 | $10,500.00 |
| 1,000 | $18.5 | $18,500.00 |
Drop-in alternatives for EPM9560RI304-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RI304-15
✅ Drop-In✓ In Stock
$112 / Unit
View Datasheet →EPM9560RI304-15N
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$88.75 / Unit
View Datasheet →EPM9560RC304-20
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Contact for price
View Datasheet →EPM9560RC304-20N
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View Datasheet →EPM9560RC304-20C
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$162 / Unit
View Datasheet →EPM9560RC304-15
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$9.4 / Unit
View Datasheet →EPM9560RI304-20 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation |
| Macrocell Count | 560 |
| Logic Array Blocks (LABs) | 16 (max) |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Maximum User I/O Pins | 212 |
| Supply Voltage (VCC) | 5.0 V |
| Programmable Technology | CMOS EEPROM |
| In-System Programmability | Yes, via JTAG (IEEE 1149.1) |
| Boundary Scan | IEEE Std. 1149.1 JTAG |
| Package | 304-pin RQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Reprogram Cycles | 100+ (EEPROM) |
EPM9560RI304-20 304-pin rqfp (plastic quad flat pack) Pin Configuration Guide
Complete pinout information for EPM9560RI304-20 (304-pin rqfp (plastic quad flat pack) package) with 212 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RI304-20.
Refer to the datasheet for full pin configuration.
Estimated pin count: 212 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI304-20 is suitable for 6 applications: High-Speed Bus Glue Logic, State Machine and Reset Controller, Peripheral Interface Bridge, Industrial Control and Automation, Legacy Telecom Backplane Logic, Test and Measurement Instrumentation.
High-Speed Bus Glue Logic
The EPM9560RI304-20 is well suited to bus-bridging glue logic between legacy 5 V buses such as PCI, VME, ISA, and proprietary backplanes. Its 560 macrocells and 212 user I/O pins allow a single device to consolidate address decoding, wait-state generation, chip-select logic, and bus arbitration that previously required multiple PAL/GAL devices. The 20 ns pin-to-pin delay comfortably meets 33 MHz PCI timing budgets, and the non-volatile EEPROM bitstream means the bus bridge is active at power-on with no PROM load latency, which is essential for boot firmware and POST logic. Compared to an FPGA alternative, this CPLD eliminates the need for an external configuration memory and provides deterministic latency for bus-arbitration paths.
Recommended
State Machine and Reset Controller
With 560 macrocells across 16 LABs, the EPM9560RI304-20 can encode complex multi-state sequencers such as power-up reset controllers, watchdog handlers, and system-health monitors. The deterministic tPD of 20 ns guarantees a known worst-case response time from a fault input to the corresponding reset assertion - critical for safety-relevant systems where asynchronous FPGA fabric would introduce unpredictable latency. The MAX 9000 LAB/macrocell architecture is well suited to wide registered state machines with many state bits and decoded outputs. The 5 V I/O is directly compatible with TTL and legacy CMOS logic in industrial control cabinets.
Recommended
Peripheral Interface Bridge
The EPM9560RI304-20 is widely deployed as a peripheral bridge between asynchronous buses such as connecting an MCU local bus to an external SRAM bank, or translating between Z80, 68000, and ARM-style handshakes. Its 212 user I/O pins provide ample headroom for parallel data paths plus chip selects, read/write strobes, and interrupt lines. The 5 V-tolerant I/Os interface directly with 5 V peripherals without level shifters, simplifying PCB layout and BOM cost. The instant-on behavior ensures the bridge is ready before the host CPU begins its first bus cycle, removing a class of boot-time race conditions common with SRAM-based FPGAs.
Recommended
Industrial Control and Automation
Industrial PLCs, motor controllers, and process automation racks benefit from the EPM9560RI304-20's robustness, deterministic timing, and high I/O count. The 5 V I/O interfaces directly to 24 V-tolerant opto-isolated inputs and relay-driver outputs common in factory equipment, while the 560 macrocells encode ladder-logic-equivalent decision trees and encoder/decoder blocks. The industrial-grade temperature rating makes it suitable for cabinet environments up to 85C. Its JTAG (IEEE 1149.1) boundary-scan support simplifies in-circuit test for densely populated backplanes where bed-of-nails probing is impractical.
Recommended
Legacy Telecom Backplane Logic
Telecom equipment designed in the late 1990s and early 2000s uses the EPM9560RI304-20 for TDM bus arbitration, framing, and protocol conversion on H.110-style CT (Computer Telephony) backplanes. Its 560 macrocells support multi-channel framers and HDLC controllers, while 212 I/Os accommodate 32-bit parallel TDM streams plus housekeeping signals. The 5 V supply matches the telecom-standard -48 V rectifier output rails. Although newer designs have migrated to FPGAs, thousands of installed systems still rely on the EPM9560RI304-20, making it a long-tail spare-parts requirement in telecom service networks.
Recommended
Test and Measurement Instrumentation
Bench-top and ATE-class test equipment uses the EPM9560RI304-20 to implement flexible stimulus generators, pattern sequencers, and front-panel I/O scanners. The 20 ns resolution enables precise timing for digital stimulus, while the 212 I/Os drive multi-channel pin electronics. The EEPROM-based bitstream allows field reconfiguration of test patterns without sending the instrument back to the factory, supporting long product lifecycles. JTAG scan chains also enable structural board-test integration, which is valuable for production-line ATE workflows.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI304-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI304-15 | EPM9560RI304-15N | EPM9560RC304-20 | EPM9560RC304-20N | EPM9560RC304-20C | EPM9560RC304-15 |
|---|---|---|---|---|---|---|---|
| Package | 304-pin RQFP | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocell Count | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 20 ns | 15 ns (faster) | 15 ns (faster) | 20 ns (same) | 20 ns (same) | 20 ns (same) | 15 ns (faster) |
| Temperature Grade | Industrial (-40C to +85C) | Industrial | Industrial, lead-free | Commercial (0 to +70C) | Commercial, lead-free | Commercial | Commercial |
| Maximum User I/O | 212 | 212 | 212 | 212 | 212 | 212 | 212 |
| Programmable Technology | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM | CMOS EEPROM |
| Lead-Free (N suffix) | No (industrial variant, tin-lead) | No | Yes | No | Yes | No | No |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest macrocell density in 304-pin RQFP (vs EPM9320RI208-20)
- Industrial temperature grade with same die as commercial parts (vs EPM9560RC304-20)
- True drop-in 304-pin RQFP footprint across speed grades (vs EPM9560RI304-15)
Design Notes
The EPM9560RI304-20 operates from a single 5.0 V supply. Place a 0.1 uF ceramic decoupling capacitor close to each VCC pin and a single 10 uF bulk tantalum or aluminum polymer capacitor near the package. The MAX 9000 family draws transient current during in-system programming; bulk capacitance prevents VCC droop that could trigger brown-out during ISP. For multi-board systems sharing a 5 V rail, add ferrite beads to isolate the CPLD's switching noise from analog circuitry.
The 304-pin RQFP has a 0.5 mm or 0.8 mm pitch (verify against datasheet pin-out); allocate at least 4 PCB layers with dedicated ground and power planes to keep loop inductance low. Route all JTAG signals (TMS, TCK, TDI, TDO) as a daisy chain with 10 kohm pull-ups on TMS and TDI per IEEE 1149.1. Keep JTAG traces short and away from switching signals to preserve signal integrity for in-system programming and boundary-scan test.
Estimated: in-system programming via JTAG requires the device's VCC to be stable for at least 100 ms after POR before programming is attempted. Do not exceed the maximum I/O pin count of 212 - assigning more than 212 user I/Os will route-fail at compile time. The EEPROM bitstream retains configuration for 20+ years but supports only ~100 reprogram cycles; design the firmware update flow to avoid excessive ISP cycles during production test.
Compliance Information
Operating temperature grade and RoHS/lead-free status require verification against the specific manufacturer datasheet revision; N-suffix variants are lead-free per Altera naming convention. Not AEC-Q100 qualified; this part targets industrial/consumer, not automotive.
