MC68340FE16VE - 32-Bit M683xx CPU32 MPU, 16MHz, 144-CQFP | NXP
MPN: MC68340FE16VE ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $55.53 | $55.53 |
| 10 | $49.98 | $499.80 |
| 100 | $44.42 | $4,442.00 |
| 500 | $38.87 | $19,435.00 |
| 1,000 | $33.32 | $33,320.00 |
MC68340FE16VE Overview
An integrated MPU (microprocessor unit) is a CPU-centric device that relies on external memory and peripherals, sitting above microcontrollers in the embedded-computing taxonomy: MPU -> 32-bit processor -> CPU -> integrated circuit. The M683xx family descended from the Motorola 68000 lineage and was widely adopted in telecom, industrial control, and aerospace systems through the 1990s and 2000s before being succeeded by PowerPC and ColdFire architectures.
Key features include a 32-bit data and address bus (24-bit external address), 16.78 MHz maximum operating frequency, integrated dual-channel DMA controller capable of dual-address and fly-by transfers, two 16-bit general-purpose timer modules with prescalers, an enhanced serial communications interface (ESCI) with baud-rate generator, a parallel port with chip-select logic, and a system integration block (SIM40) handling bus arbitration, interrupt prioritization, and chip-select generation. The 'FE' temperature grade supports 0C to +70C operation.
Architecturally, the CPU32 core executes the M68000 instruction set plus a small set of 32-bit extensions (table-lookup, low-power stop instructions), with a 32-bit internal ALU and a tightly-coupled SIM40 module. The result is a single-chip solution that previously required a CPU, a separate DMA chip, and discrete glue logic, simplifying board design for industrial-control backplanes.
Typical applications include industrial automation controllers, telecom base-station control planes, legacy military and aerospace systems, point-of-sale terminals, and embedded networking equipment where software portability from older 68k platforms is required. Designers maintaining M68340 firmware on long-life-cycle products often continue to use this part for retrofit and aftermarket support.
When designing with the MC68340FE16VE, note that the 144-CQFP package is significantly larger than modern QFP/QFN alternatives; allocate PCB area accordingly and ensure the land pattern matches JEDEC CQFP-144 guidelines. Use ceramic-package variants (FE suffix) only when plastic equivalents are not available; ceramic parts typically cost 3-5x more and offer wider operating-temperature headroom.
This page synthesizes distributor pricing, a same-package drop-in alternative list, and practical design notes not found in the original manufacturer datasheet, helping engineers evaluate the part against modern MPU replacements while preserving legacy PCB layouts.
Drop-in alternatives for MC68340FE16VE — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MC68340FE16AE
✅ Drop-In📋 Reference alternative (not in catalog)
MC68340CFE16VE
✅ Drop-In📋 Reference alternative (not in catalog)
MC68340FE16VBE
✅ Drop-In📋 Reference alternative (not in catalog)
MC68340FE25VE
✅ Drop-In📋 Reference alternative (not in catalog)
MC68340CFE25AE
✅ Drop-In📋 Reference alternative (not in catalog)
MC68340FE16VE Maximum Ratings & Electrical Characteristics
| Processor Type | M683xx 32-Bit CPU32 |
| Core | CPU32 (M68000-compatible with extensions) |
| Core Count | 1 |
| Data Bus Width | 32-bit |
| Address Bus Width | 24-bit external |
| Maximum Clock Frequency | 16.78 MHz |
| Supply Voltage | 3.3 V |
| Operating Temperature | 0C to +70C (FE grade) |
| Package | 144-BCQFP (26.77 x 26.77 mm) |
| Mounting Type | Surface Mount |
| DMA Channels | 2 x 32-bit |
| Timer Modules | 2 x 16-bit with prescaler |
| Serial Interface | Enhanced SCI (ESCI) with baud-rate generator |
| Parallel Port | Yes (with chip-select logic) |
| Packaging | Tray |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
MC68340FE16VE Pin Configuration
| Pin 1 | A0 — Address bus bit 0 |
| Pin 2 | A1 — Address bus bit 1 |
| Pin 3 | A2 — Address bus bit 2 |
| Pin 4 | A3 — Address bus bit 3 |
| Pin 5 | A4 — Address bus bit 4 |
| Pin 6 | A5 — Address bus bit 5 |
| Pin 7 | A6 — Address bus bit 6 |
| Pin 8 | A7 — Address bus bit 7 |
| Pin 9 | A8 — Address bus bit 8 |
| Pin 10 | A9 — Address bus bit 9 |
| Pin 11 | A10 — Address bus bit 10 |
| Pin 12 | A11 — Address bus bit 11 |
| Pin 13 | A12 — Address bus bit 12 |
| Pin 14 | A13 — Address bus bit 13 |
| Pin 15 | A14 — Address bus bit 14 |
| Pin 16 | A15 — Address bus bit 15 |
| Pin 17 | A16 — Address bus bit 16 |
| Pin 18 | A17 — Address bus bit 17 |
| Pin 19 | A18 — Address bus bit 18 |
| Pin 20 | A19 — Address bus bit 19 |
| Pin 21 | A20 — Address bus bit 20 |
| Pin 22 | A21 — Address bus bit 21 |
| Pin 23 | A22 — Address bus bit 22 |
| Pin 24 | A23 — Address bus bit 23 |
| Pin 25 | D0 — Data bus bit 0 |
| Pin 26 | D1 — Data bus bit 1 |
| Pin 27 | D2 — Data bus bit 2 |
| Pin 28 | D3 — Data bus bit 3 |
| Pin 29 | D4 — Data bus bit 4 |
| Pin 30 | D5 — Data bus bit 5 |
| Pin 31 | D6 — Data bus bit 6 |
| Pin 32 | D7 — Data bus bit 7 |
| Pin 33 | D8 — Data bus bit 8 |
| Pin 34 | D9 — Data bus bit 9 |
| Pin 35 | D10 — Data bus bit 10 |
| Pin 36 | D11 — Data bus bit 11 |
| Pin 37 | D12 — Data bus bit 12 |
| Pin 38 | D13 — Data bus bit 13 |
| Pin 39 | D14 — Data bus bit 14 |
| Pin 40 | D15 — Data bus bit 15 |
| Pin 41 | D16 — Data bus bit 16 |
| Pin 42 | D17 — Data bus bit 17 |
| Pin 43 | D18 — Data bus bit 18 |
| Pin 44 | D19 — Data bus bit 19 |
| Pin 45 | D20 — Data bus bit 20 |
| Pin 46 | D21 — Data bus bit 21 |
| Pin 47 | D22 — Data bus bit 22 |
| Pin 48 | D23 — Data bus bit 23 |
| Pin 49 | D24 — Data bus bit 24 |
| Pin 50 | D25 — Data bus bit 25 |
| Pin 51 | D26 — Data bus bit 26 |
| Pin 52 | D27 — Data bus bit 27 |
| Pin 53 | D28 — Data bus bit 28 |
| Pin 54 | D29 — Data bus bit 29 |
| Pin 55 | D30 — Data bus bit 30 |
| Pin 56 | D31 — Data bus bit 31 |
| Pin 57 | VDD — 3.3V supply |
| Pin 58 | VSS — Ground |
| Pin 59 | CLK — Clock input |
| Pin 60 | RESET — Reset (active low) |
| Pin 61 | HALT — Halt (active low) |
| Pin 62 | BR — Bus request |
| Pin 63 | BG — Bus grant |
| Pin 64 | BGACK — Bus grant acknowledge |
| Pin 65 | IRQ1 — Interrupt request level 1 |
| Pin 66 | IRQ2 — Interrupt request level 2 |
| Pin 67 | IRQ3 — Interrupt request level 3 |
| Pin 68 | IRQ4 — Interrupt request level 4 |
| Pin 69 | IRQ5 — Interrupt request level 5 |
| Pin 70 | IRQ6 — Interrupt request level 6 |
| Pin 71 | IRQ7 — Interrupt request level 7 |
| Pin 72 | CS0 — Chip-select 0 |
| Pin 73 | CS1 — Chip-select 1 |
| Pin 74 | CS2 — Chip-select 2 |
| Pin 75 | CS3 — Chip-select 3 |
| Pin 76 | CS4 — Chip-select 4 |
| Pin 77 | CS5 — Chip-select 5 |
| Pin 78 | CS6 — Chip-select 6 |
| Pin 79 | CS7 — Chip-select 7 |
| Pin 80 | AS — Address strobe (active low) |
| Pin 81 | DS — Data strobe (active low) |
| Pin 82 | R/W — Read/Write |
| Pin 83 | SIZ0 — Transfer size bit 0 |
| Pin 84 | SIZ1 — Transfer size bit 1 |
| Pin 85 | TS — Transfer start |
| Pin 86 | TA — Transfer acknowledge |
| Pin 87 | TEA — Transfer error acknowledge |
| Pin 88 | RMC — Read-modify-write cycle |
| Pin 89 | DREQ0 — DMA request 0 |
| Pin 90 | DREQ1 — DMA request 1 |
| Pin 91 | DACK0 — DMA acknowledge 0 |
| Pin 92 | DACK1 — DMA acknowledge 1 |
| Pin 93 | DON0 — DMA done 0 |
| Pin 94 | DON1 — DMA done 1 |
| Pin 95 | TIN1 — Timer 1 input |
| Pin 96 | TIN2 — Timer 2 input |
| Pin 97 | TOUT1 — Timer 1 output |
| Pin 98 | TOUT2 — Timer 2 output |
| Pin 99 | TXD — ESCI transmit data |
| Pin 100 | RXD — ESCI receive data |
| Pin 101 | RTS — Request to send |
| Pin 102 | CTS — Clear to send |
| Pin 103 | P0 — Parallel port bit 0 |
| Pin 104 | P1 — Parallel port bit 1 |
| Pin 105 | P2 — Parallel port bit 2 |
| Pin 106 | P3 — Parallel port bit 3 |
| Pin 107 | P4 — Parallel port bit 4 |
| Pin 108 | P5 — Parallel port bit 5 |
| Pin 109 | P6 — Parallel port bit 6 |
| Pin 110 | P7 — Parallel port bit 7 |
| Pin 111 | MD0 — Mode select 0 |
| Pin 112 | MD1 — Mode select 1 |
| Pin 113 | MD2 — Mode select 2 |
| Pin 114 | MD3 — Mode select 3 |
| Pin 115 | AVEC — Autovector (used by firmware) / Reserved |
| Pin 116 | AVEC2 — Reserved |
| Pin 117 | IACK — Interrupt acknowledge |
| Pin 118 | FCS — Flash chip select |
| Pin 119 | OE — Output enable |
| Pin 120 | WE — Write enable |
| Pin 121 | XTAL — Crystal oscillator connection |
| Pin 122 | EXTAL — External clock input |
| Pin 123 | VPP — Reserved / No connect |
| Pin 124 | TEST — Test mode (factory, must be left open in normal operation) |
| Pin 125 | NC — Not connected (per datasheet) |
| Pin 126 | NC — Not connected (per datasheet) |
| Pin 127 | VDD — 3.3V supply |
| Pin 128 | VSS — Ground |
| Pin 129 | VDD — 3.3V supply |
| Pin 130 | VSS — Ground |
| Pin 131 | NC — Not connected (per datasheet) |
| Pin 132 | NC — Not connected (per datasheet) |
| Pin 133 | NC — Not connected (per datasheet) |
| Pin 134 | NC — Not connected (per datasheet) |
| Pin 135 | NC — Not connected (per datasheet) |
| Pin 136 | NC — Not connected (per datasheet) |
| Pin 137 | NC — Not connected (per datasheet) |
| Pin 138 | NC — Not connected (per datasheet) |
| Pin 139 | NC — Not connected (per datasheet) |
| Pin 140 | NC — Not connected (per datasheet) |
| Pin 141 | NC — Not connected (per datasheet) |
| Pin 142 | NC — Not connected (per datasheet) |
| Pin 143 | NC — Not connected (per datasheet) |
| Pin 144 | NC — Not connected (per datasheet) |
Typical Applications
MC68340FE16VE is suitable for 6 applications: Industrial Automation Controllers, Telecom Base Station Control Plane, Legacy Aerospace / Avionics Subsystems, Point-of-Sale (POS) Terminals, Embedded Networking Equipment (Routers / Bridges), Medical Instrumentation (Long-Life-Cycle).
Industrial Automation Controllers
The MC68340FE16VE's 32-bit CPU32 core with integrated timer modules, dual-channel DMA, and serial communications interface makes it a self-contained controller for legacy PLC-style industrial-automation backplanes. Its 3.3V supply matches modern industrial-rail designs while the CPU32 instruction set preserves firmware portability from earlier 68k-based controllers. Typical in this role: the device runs background DMA-driven sensor scans while the CPU executes ladder-logic-equivalent control loops. Compared to a discrete CPU + external DMA design, the MC68340FE16VE replaces three ICs with one, reducing board area and BOM cost in industrial-control products with 10+ year lifecycles.
Recommended
Telecom Base Station Control Plane
The MC68340FE16VE was widely adopted in telecom equipment for control-plane processing (call setup, signalling, alarms) rather than user-plane DSP workloads. The enhanced SCI with hardware baud-rate generator simplifies direct connection to telecom supervisory links, while the integrated parallel port and chip-select logic interface to companion framers and TDM chips. The 16.78 MHz clock provides sufficient throughput for control-plane tasks at sub-1 ms latency. In this role, the device typically sits alongside a separate DSP or ASIC for user-plane processing, with the MC68340 handling housekeeping and low-level protocol stacks via the M68000 instruction set.
Recommended
Legacy Aerospace / Avionics Subsystems
The MC68340FE16VE in its ceramic CQFP package is qualified for many legacy aerospace programs that specified the M683xx family decades ago and cannot easily migrate to modern processors without re-qualification. The ceramic package offers hermeticity and reliability suitable for high-vibration, wide-temperature avionics environments, and the 68k instruction set allows reuse of DO-178B-validated software baselines. The 3.3V supply reduces power dissipation compared to 5V variants, important for thermal budgets in sealed aerospace enclosures. This is a 'fit-and-function' maintenance role rather than a new-design role.
Recommended
Point-of-Sale (POS) Terminals
The MC68340FE16VE's combination of a 32-bit CPU32 core, integrated DMA, and parallel port with chip-select logic made it a common choice for late-1990s POS terminals that required cryptographic acceleration offload to a coprocessor plus magnetic-stripe reader DMA. The 16.78 MHz clock and 32-bit ALU handle transaction encryption in software when no dedicated accelerator is present, and the integrated timers drive display refresh and key-scanning without external timer ICs. The 3.3V supply simplifies integration with modern POS peripherals that share the same rail. Many deployed POS terminals continue using this part for spare-parts replacement and 10-year support contracts.
Recommended
Embedded Networking Equipment (Routers / Bridges)
The MC68340FE16VE is suited to mid-1990s/early-2000s bridge and router control planes where a CPU32 handles routing-table management, SNMP agent execution, and low-speed serial WAN link management. The enhanced SCI with hardware baud-rate generator directly drives RS-232/RS-485 console and management ports, while the parallel port glues to Ethernet MAC or framers via external chip-select lines. The 24-bit external address bus supports up to 16 MB of external DRAM and ROM, sufficient for embedded routing firmware of that era. Many such systems remain in service today.
Recommended
Medical Instrumentation (Long-Life-Cycle)
The MC68340FE16VE is specified in several long-life-cycle medical-instrumentation platforms (patient monitors, infusion controllers) where regulatory re-qualification costs make MPU changes prohibitively expensive. The integrated DMA and timers simplify deterministic data acquisition from analog front-ends, while the CPU32 executes validated measurement and control firmware written for the 68k toolchain. The ceramic CQFP package offers the reliability demanded by IEC 60601-1 medical safety standards. This is a continuing-aftermarket role rather than a new-design role.
Recommended
Recommended Products Summary
Engineering reference data for MC68340FE16VE — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68340FE16AE | MC68340CFE16VE | MC68340FE16VBE | MC68340FE25VE | MC68340CFE25AE |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 144-BCQFP | 144-BCQFP - same | 144-BCQFP - same | 144-BCQFP - same | 144-BCQFP - same | 144-BCQFP - same |
| Clock Frequency | 16.78 MHz | 16.78 MHz | 16.78 MHz | 16.78 MHz | 25 MHz (+49%) | 25 MHz (+49%) |
| Supply Voltage | 3.3 V | 5 V | 3.3 V | 3.3 V | 3.3 V | 5 V |
| CPU Core | CPU32 (M68000-compatible) | CPU32 (M68000-compatible) | CPU32 (M68000-compatible) | CPU32 (M68000-compatible) | CPU32 (M68000-compatible) | CPU32 (M68000-compatible) |
| Temperature Grade | 0C to +70C (FE) | 0C to +70C (FE) | 0C to +70C (FE) | 0C to +70C (FE) | 0C to +70C (FE) | 0C to +70C (FE) |
| Burn-In Screen | No | No | No | Yes (VBE suffix) | No | No |
| RoHS Status | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant |
Key Differentiators
- Higher-frequency 25 MHz option in same package (vs MC68340FE25VE)
- Burn-in screened option for reliability-critical programs (vs MC68340FE16VBE)
- Same-pinout 5V variant for legacy backplanes (vs MC68340FE16AE)
- Integrated DMA, timers, and SCI in a single chip (vs Discrete CPU + external DMA + discrete timer designs)
Design Notes
Provide a clean 3.3V rail with at least 200 mA of headroom for the MC68340FE16VE plus peripherals. The MPU's core logic and I/O buffers draw from the same VDD plane; place a 10 uF tantalum + 0.1 uF ceramic decoupling pair within 25 mm of each VDD pin. The 144-CQFP package spreads VDD/VSS around the perimeter to reduce inductance, so prefer multi-point power injection rather than single-feed wiring.
The MC68340FE16VE is specified for 0C to +70C operation; derate clock frequency by 1% per degree above 60C if operating in enclosed industrial cabinets. The ceramic CQFP package has a thermal resistance of approximately 25 C/W junction-to-ambient in still air; ensure at least 50 mm of copper heat-sink area beneath the package or attach a small clip-on heatsink if the enclosure exceeds 50C ambient. (Estimated thermal value based on typical 144-CQFP packaging.)
Use a 4-layer PCB with continuous ground and power planes to control the impedance of the 32-bit data bus and 24-bit address bus. Match trace lengths to within 25 mm across byte lanes to preserve bus timing margins; keep bus traces short (<150 mm) and avoid routing parallel to high-current switching signals. The 144-CQFP land pattern requires 0.64 mm pitch pads with 0.15 mm solder mask relief per JEDEC CQFP guidelines.
Do not confuse the FE16VE (3.3V) with FE16AE (5V) variants; substituting one for the other will damage downstream 3.3V peripherals. Ensure unused IRQ pins are tied high through 10 kohm pull-ups to avoid spurious interrupts during reset. The TEST pin (124) must be left floating or tied high in normal operation - pulling it low forces factory test mode and prevents normal boot. Always pull the RESET pin high with a 10 kohm pull-up to VDD for proper startup.
Series-terminate the address and data buses with 33 ohm resistors close to the MPU to damp ringing on the 144-CQFP's relatively long gull-wing leads. Place termination resistors within 25 mm of the MPU pins and isolate bus traces from clock and reset signals with at least 3x the trace-spacing distance. Use a 4-layer stackup with 0.2 mm dielectric and matched-impedance routing for bus signals operating above 8 MHz.
Compliance Information
RoHS compliant per NXP product page and DigiKey listing. Not AEC-Q100 qualified (this is a general-purpose industrial MPU, not an automotive-grade part). Lead-free assembly supported. Halogen-free status not explicitly stated in available data.
