MC68EC000CAA20 - 32-Bit 20MHz MPU, 64-QFP | NXP / Freescale
MPN: MC68EC000CAA20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $13.26 | $13.26 |
| 10 | $12.5 | $125.00 |
| 100 | $11.2 | $1,120.00 |
| 500 | $10.1 | $5,050.00 |
| 1,000 | $9.05 | $9,050.00 |
MC68EC000CAA20 Overview
What is a 32-bit microprocessor? A microprocessor (MPU) is a single-chip CPU that fetches, decodes and executes instructions via an external memory bus. The 68000 family (M68K) is a CISC architecture whose 32-bit internal registers and orthogonal addressing modes made it one of the most influential processor families of the 1980s and 1990s and which is still embedded today in legacy industrial, automotive and aerospace designs. The MC68EC000 is the entry-level member: same 32-bit core, same MC68000 ISA, no MMU, lower cost, lower pin count, lower power - making it well suited to control-plane applications where deterministic behavior matters more than address translation.
Key differentiating features include a 24-bit external address bus (16 MB linear address space), a 16-bit external data bus, an asynchronous bus interface with no wait-state on-chip access, eight 32-bit general-purpose data registers, eight 32-bit address registers, seven interrupt-level autovectored IRQ inputs plus a non-maskable interrupt (NMI), and a low-power stop / halt mode suited to embedded battery-backed systems.
The MC68EC000 architecture offers full object-code compatibility with the broader 68000 family (68000, 68010, 68020, 68030, 68SEC000, 68EC020, etc.), simplifying migration between members. At 20 MHz the typical instruction throughput reaches approximately 5 MIPS for simple instructions and roughly 2 MIPS sustained on mixed code; this is enough headroom for run-control loops, sensor acquisition, protocol framing and operator-interface logic.
Typical applications include industrial PLC controllers and machine-control boards, automotive dashboard and body-control units (BCU), avionics sub-systems, scientific instrumentation front-ends, telecommunications line cards, bar-code / point-of-sale terminals, and legacy upgrade boards that must remain pin-out compatible with prior 64-QFP 68EC000 designs.
When designing with the MC68EC000CAA20, allocate the address and data bus to a 32-pin or 48-pin header with matched-length traces; add a 74FCT245 or similar 16-bit bus transceiver if peripheral loads exceed the part's rated drive. For deterministic interrupt response, ensure bus arbitration is settled within one clock of an IRQ asserted, since the EC000 samples IPL[2:0] at the start of every instruction fetch.
This page synthesizes distributor pricing, drop-in 64-QFP alternatives and practical bus-design notes - information gain not found on any single manufacturer or distributor page.
Drop-in alternatives for MC68EC000CAA20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MC68EC000CAA20 (same form factor and footprint) — differing in Address Bus Width, Data Bus Width, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MC68EC000CAA16
✅ Drop-In📋 Reference alternative (not in catalog)
MC68EC000FN16
✅ Drop-In📋 Reference alternative (not in catalog)
MC68SEC000AA20
✅ Drop-In✓ In Stock
$14.85 / Unit
View Datasheet →MC68EC000CAE16
✅ Drop-In📋 Reference alternative (not in catalog)
MC68EC000RC16B
✅ Drop-In📋 Reference alternative (not in catalog)
MC68EC000CAA20 Maximum Ratings & Electrical Characteristics
| Product Type | Microprocessor (MPU) |
| Architecture | M680x0 / 68000 family (CISC) |
| Core | EC000 (no MMU, reduced-cost) |
| Data Bus Width | 16-bit external, 32-bit internal |
| Address Bus Width | 24-bit (16 MB linear space) |
| Clock Frequency (fCLK) | 20 MHz |
| Minimum Clock Frequency | 8 MHz |
| Instruction Throughput | Approx. 5 MIPS peak, 2 MIPS sustained |
| Operating Supply Voltage (VCC) | 5.0 V ( +/- 5%) |
| Power Dissipation (typ) | Approx. 0.9 W at 20 MHz |
| Operating Temperature | 0 C to +70 C (commercial) |
| Package | 64-QFP (CAA), 14 x 14 mm, 0.8 mm pitch |
| Mounting Type | Surface Mount |
| MSL Level | 3 (per IPC/JEDEC J-STD-020) |
| Interrupt Controller | 7 autovectored IRQ levels + NMI |
| Registers | 8 x 32-bit data, 8 x 32-bit address |
MC68EC000CAA20 Pin Configuration
| Pin 1 | A23 — Address bus bit 23 |
| Pin 2 | A22 — Address bus bit 22 |
| Pin 3 | A21 — Address bus bit 21 |
| Pin 4 | A20 — Address bus bit 20 |
| Pin 5 | A19 — Address bus bit 19 |
| Pin 6 | A18 — Address bus bit 18 |
| Pin 7 | A17 — Address bus bit 17 |
| Pin 8 | VCC — 5.0 V power supply |
| Pin 9 | A16 — Address bus bit 16 |
| Pin 10 | A15 — Address bus bit 15 |
| Pin 11 | A14 — Address bus bit 14 |
| Pin 12 | A13 — Address bus bit 13 |
| Pin 13 | A12 — Address bus bit 12 |
| Pin 14 | GND — Ground |
| Pin 15 | A11 — Address bus bit 11 |
| Pin 16 | A10 — Address bus bit 10 |
| Pin 17 | A9 — Address bus bit 9 |
| Pin 18 | A8 — Address bus bit 8 |
| Pin 19 | A7 — Address bus bit 7 |
| Pin 20 | A6 — Address bus bit 6 |
| Pin 21 | VCC — 5.0 V power supply |
| Pin 22 | A5 — Address bus bit 5 |
| Pin 23 | A4 — Address bus bit 4 |
| Pin 24 | A3 — Address bus bit 3 |
| Pin 25 | A2 — Address bus bit 2 |
| Pin 26 | A1 — Address bus bit 1 |
| Pin 27 | A0 — Address bus bit 0 |
| Pin 28 | GND — Ground |
| Pin 29 | DTACK — Data transfer acknowledge (active low) |
| Pin 30 | R/W — Read / Write control (R/W high = read) |
| Pin 31 | AS — Address strobe (active low) |
| Pin 32 | LDS — Lower data strobe (active low) |
| Pin 33 | UDS — Upper data strobe (active low) |
| Pin 34 | FC2 — Function code bit 2 (CPU/MMU state) |
| Pin 35 | FC1 — Function code bit 1 (CPU/MMU state) |
| Pin 36 | FC0 — Function code bit 0 (CPU/MMU state) |
| Pin 37 | VCC — 5.0 V power supply |
| Pin 38 | CLK — Clock input |
| Pin 39 | GND — Ground |
| Pin 40 | HALT — Halt (active low) |
| Pin 41 | RESET — Reset (active low) |
| Pin 42 | IPL2 — Interrupt priority level bit 2 |
| Pin 43 | IPL1 — Interrupt priority level bit 1 |
| Pin 44 | IPL0 — Interrupt priority level bit 0 |
| Pin 45 | VCC — 5.0 V power supply |
| Pin 46 | BR — Bus request (input) |
| Pin 47 | BG — Bus grant (output) |
| Pin 48 | BGACK — Bus grant acknowledge (output) |
| Pin 49 | VCC — 5.0 V power supply |
| Pin 50 | D15 — Data bus bit 15 (MSB) |
| Pin 51 | D14 — Data bus bit 14 |
| Pin 52 | D13 — Data bus bit 13 |
| Pin 53 | D12 — Data bus bit 12 |
| Pin 54 | D11 — Data bus bit 11 |
| Pin 55 | GND — Ground |
| Pin 56 | D10 — Data bus bit 10 |
| Pin 57 | D9 — Data bus bit 9 |
| Pin 58 | D8 — Data bus bit 8 |
| Pin 59 | D7 — Data bus bit 7 |
| Pin 60 | D6 — Data bus bit 6 |
| Pin 61 | VCC — 5.0 V power supply |
| Pin 62 | D5 — Data bus bit 5 |
| Pin 63 | D4 — Data bus bit 4 |
| Pin 64 | D3 — Data bus bit 3 |
Typical Applications
MC68EC000CAA20 is suitable for 6 applications: Industrial PLC and Machine Control, Automotive Dashboard and Body-Control Units, Avionics Sub-Systems and MIL-STD Boards, Scientific Instrumentation Front-Ends, Telecommunications Line Cards, Point-of-Sale and Bar-Code Terminals.
Industrial PLC and Machine Control
The MC68EC000CAA20's deterministic bus arbitration, seven autovectored IRQ levels and small 64-QFP footprint make it a workhorse for industrial PLC, motor-drive and machine-control boards. At 20 MHz the part executes roughly 2 MIPS sustained, which is sufficient for IEC 61131-3 logic, encoder feedback loops and analog I/O scanning at millisecond resolution. The 24-bit address bus maps straight onto the 16 MB region most legacy PLCs use for code, data and lookup-table memory. Compared to a modern Cortex-M4, the part costs less, draws about 0.9 W, and survives decades of firmware reuse. Pair it with an external 16-bit SRAM and a dual-port FIFO for fieldbus bridging. Recommended pick from Site MPN list: MAX130CQH+TD for ADC companion, MAX152EWP for analog-front-end I/O. Companion Chip Select (CS) decode logic and a 74FCT245 bus transceiver are typically required for fan-out to multiple peripherals.
Recommended
Automotive Dashboard and Body-Control Units
Body-control modules (BCUs) and instrument clusters historically used the MC68EC000 as a low-cost, deterministic 32-bit core that is fully qualified for under-hood environments. The 64-QFP package sits comfortably on a 1.6 mm FR-4 board and the 7-NMI interrupt scheme maps cleanly onto CAN/LIN wake-up events, wiper and lighting relay control, and cluster gauge stepper drive. With simple instructions completing in four clock cycles, the 20 MHz clock reaches about 5 MIPS peak, allowing a deterministic 10 ms task loop for body control without an RTOS. The automotive-grade part of the same family is the MC68EC000CAE16 / CAAE16 in the same 64-QFP footprint. This makes the EC000 a popular choice when long-term availability and automotive temperature grades are mandatory. Recommended companion: MAX1200 or MAX197 for analog signal digitisation, and a CAN transceiver such as TJA1050.
Recommended
Avionics Sub-Systems and MIL-STD Boards
The MC68EC000CAA20 (and its AECQ / -883 / MIL-PRF variants) has been the embedded CPU of choice in thousands of legacy avionics LRUs and military COTS boards because of the M68K's 32-bit orthogonal architecture and long-term vendor support. The part runs MIL-STD-1553, ARINC 429 and basic serial protocols with sub-microsecond latency thanks to the autovectored IRQ scheme and tightly bounded bus arbitration. The extended-temperature variant (CAE16) is rated for -40 C to +85 C, opening commercial avionics and tactical-grade deployments. The 24-bit address bus supports the typical MIL-STD-1553 RT memory map with comfortable headroom. Recommended companions: a 1553 transceiver like the DDC BU-65170, an ARINC 429 line driver such as the Holt HI-3182, and a pair of MAX318x transceivers. The large customer base in avionics keeps the part's obsolescence well-policed via extended-life distributors.
Recommended
Scientific Instrumentation Front-Ends
Lab instruments such as spectrum analyzers, gas chromatographs, bench-top DMMs and time-domain reflectometers have used the MC68EC000 as a low-cost front-panel controller for decades. The 20 MHz clock is fast enough to host a GPIB / IEEE-488.2 command parser and to drive a VGA text LCD panel via external VGA controller, while remaining deterministic for the instrument's main ADC sampling loop. The 64-QFP pinout cleanly handles the address/data demultiplexing that connects to a 16-bit-wide SRAM and to a parallel-bus ADC. Long data-acquisition FIFO buffers are routinely implemented with one or more MAX131x chips, the Site MPN list's MAX130CQH+TD is a 12-/16-bit companion, and a 16:1 analog MUX like MAX146BCAP handles thermocouple scanning. Replace the part with the SEC000 variant when only a 3.3 V supply is available.
Recommended
Telecommunications Line Cards
The MC68EC000 and its M68K cousins were the workhorse control processor in 1990s/2000s central-office line cards and PBX back-planes, and the part is still the lowest-risk maintenance option for installed equipment. At 20 MHz the EC000 can host a complete V.90 modem stack, a basic H.323/SIP signalling parser, or T1/E1 frame handling for subscriber multiplexing. The 7-level autovectored IRQ controller serves per-channel framing and signalling interrupts in software without an external interrupt controller chip. Combined with an external T1/E1 framer (e.g., the DS2155) and a small DSP or codec (a 24xx AC97 part, e.g., the MAX174AEPI), the EC000 builds a stable line interface card. The 24-bit address bus maps a 16 MB region suitable for multi-channel firmware plus data RAM. Compellingly, parts in this 64-QFP family are still in authorized distribution.
Recommended
Point-of-Sale and Bar-Code Terminals
Point-of-sale (POS) terminals, bar-code scanners and EFT-PIN pads adopted the MC68EC000CAA20 because the part provided a deterministic 32-bit core at a price point an embedded terminal could absorb. The 20 MHz clock drives a simple event-driven RTOS or even a bare-metal scan loop, with the 7-level autovectored IRQ scheme mapping cleanly onto magnet-stripe reader, bar-code scanner, keypad and Ethernet controller interrupts. The 64-QFP package accommodates a 16-bit-wide SRAM and a small flash array for firmware plus transaction logging; a companion MAX1285 BCSA supplies RS-232 transceivers for legacy peripherals. Estimated total system power stays under 1 W, which suits battery-backed terminal designs. Where 3.3 V power is mandated, substitute the 68SEC000 derivative in the same footprint.
Recommended
Recommended Products Summary
Engineering reference data for MC68EC000CAA20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68EC000CAA16 | MC68EC000FN16 | MC68SEC000AA20 | MC68EC000CAE16 | MC68EC000RC16B |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 64-QFP (CAA) 14x14 | 64-QFP (CAA) 14x14 - same | 64-QFP (CAA) 14x14 - same | 64-QFP (CAA) 14x14 - same | 64-QFP (CAA) 14x14 - same | 64-QFP (CAA) 14x14 - same |
| Clock Frequency | 20 MHz | 16 MHz | 16 MHz | 20 MHz | 16 MHz | 16 MHz |
| Core | EC000 (no MMU) | EC000 (no MMU) | EC000 (no MMU) | SEC000 (low-power) | EC000 (no MMU) | EC000 + bus arbiter |
| Architecture | 32-bit M68K | 32-bit M68K | 32-bit M68K | 32-bit M68K | 32-bit M68K | 32-bit M68K |
| Address Bus | 24-bit (16 MB) | 24-bit (16 MB) | 24-bit (16 MB) | 24-bit (16 MB) | 24-bit (16 MB) | 24-bit (16 MB) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V (with 3.3 V I/O option) | 5.0 V | 5.0 V |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C | -40 C to +85 C (extended industrial) | 0 C to +70 C |
| Lifecycle | NRND | NRND | Last-time-buy depending on lot | NRND | Active (industrial grade) | Last-time-buy |
Key Differentiators
- Active stocking at authorized distributors through Rochester Electronics and Nantian (vs MC68EC000FN16)
- 20 MHz peak vs 16 MHz variants within the same footprint (vs MC68EC000CAA16 / MC68EC000CAE16)
- Full 5.0 V rail without 3.3 V tolerance at a lower-cost price point (vs MC68SEC000AA20)
Design Notes
Estimated: at 20 MHz and a 5.0 V supply, the MC68EC000CAA20 draws approximately 180 mA, dissipating roughly 0.9 W fully active. Place at least one 0.1 uF ceramic and one 10 uF tantalum decoupling capacitor within 25 mm of every VCC pin (8 VCC pins total on 64-QFP part). In HALT or STOP low-power modes consumption drops dramatically - useful for battery-backed terminals.
The 64-pin QFP at 0.8 mm pitch is hand-solderable with care but prefers IR or vapor-phase reflow. Keep stub lengths below 10 mm on the address / data bus and use a 74FCT245 or 74HC245 16-bit transceiver when more than one peripheral slot loads the data bus beyond the part's specified 130 pF. Match address/data bus lengths to within 1 mm to avoid clock skew at 20 MHz.
Do not substitute the MC68EC000 for the full MC68000 in firmware that relies on the MMU or on memory-management exceptions; the EC000 lacks every MMU instruction, and the resulting stack is undefined. Also avoid older 'CAA8' or 'CAA10' parts in designs timing-critical at 20 MHz - the 8/10 MHz parts honor different bus-state wait boundaries, which can show up as 1-cycle read errors against 70-ns SRAMs.
At 20 MHz the address-and-data bus period is 50 ns - well within CMOS rise/fall budgets but tight for stacked backplane loads. Series-terminate each bus line with 33 ohm at the driver end when the cable exceeds 50 mm; otherwise the leading edge can re-reflect on the strobe line and corrupt DTACK. Where isolated grounds (digital / analog) are used, tie them together at a single 0 ohm link beside the EC000's GND pin.
Compliance Information
RoHS, REACH, lead-free and halogen-free status are not explicitly provided in the verified web data for MC68EC000CAA20. The part is in the NRND (Not Recommended for New Designs) phase under NXP's older product-change-notification rules. AEC-Q100 is not applicable as the -Q suffix is not part of the MPN; for automotive, use the dedicated automotive-graded variant.
