MC68SEC000FU20R2 - 32-Bit 20MHz M68000 MPU | Freescale | 64-QFP
MPN: MC68SEC000FU20R2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $22.5 | $22.50 |
| 10 | $19.95 | $199.50 |
| 100 | $17.2 | $1,720.00 |
| 500 | $14.85 | $7,425.00 |
| 1,000 | $12.95 | $12,950.00 |
MC68SEC000FU20R2 Overview
A microprocessor (MPU) is the central execution unit of an embedded computing system, fetching instructions from external program memory, decoding them, and driving peripheral controllers through address and data buses. The M68000 family occupies a well-defined place in the taxonomy: MPU -> 32-bit microprocessor -> CISC -> M68000 family -> low-power static core (68SEC000). It remains popular in legacy industrial controllers, avionics, and educational systems where software compatibility with the classic 68k instruction set is mandatory.
Key features of the MC68SEC000FU20R2 include a fully static HCMOS implementation that allows the clock to be stopped without losing internal state, support for 8-, 16-, and 32-bit data bus sizing through the S0/S1 pins, a 24-bit address bus providing 16 MByte of linear addressing, and seven autovectored interrupt levels plus a separate non-maskable interrupt. The device requires a single 5 V supply, eliminating the -12 V rail needed by the original MC68000.
From an architectural standpoint, the MC68SEC000 is a pin-compatible, low-power re-implementation of the MC68HC000, with the same instruction set, programmer's model, and memory map. Designers moving legacy 68k code to a battery-powered platform can drop the MC68SEC000FU20R2 onto an existing 64-QFP footprint without firmware changes. Typical latency-sensitive primitives (interrupt acknowledge, bus arbitration) match the HC000 cycle-for-cycle.
Typical applications include portable data-acquisition terminals, handheld industrial instruments, low-power embedded controllers, educational 68k trainer boards, and legacy avionics retrofit cards. The wide operating temperature range and static core also make it suitable for ruggedised field equipment that must idle at sub-mW levels between samples.
When designing with the MC68SEC000FU20R2, ensure the clock-stop low time does not exceed the device's static-leakage budget at elevated temperature, and add bulk decoupling near each VCC/VSS pair. Because the part is now sourced through authorised distributors and the open market rather than direct from the original manufacturer, expect longer lead times and verify date codes carefully.
This page synthesises distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found on a single manufacturer datasheet - useful for engineers maintaining legacy 68k platforms.
Drop-in alternatives for MC68SEC000FU20R2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MC68SEC000FU20R2 (same form factor and footprint) — differing in Address Bus Width.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MC68SEC000FU20
✅ Drop-In📋 Reference alternative (not in catalog)
MC68SEC000FU16
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →MC68SEC000FU10
✅ Drop-In📋 Reference alternative (not in catalog)
MC68HC000FU16
✅ Drop-In📋 Reference alternative (not in catalog)
MC68EC000FU20
✅ Drop-In📋 Reference alternative (not in catalog)
MC68SEC000FU20R2 Maximum Ratings & Electrical Characteristics
| Product Type | Microprocessor (MPU) |
| Core | M68000 (68SEC000, static HCMOS) |
| Number of Cores | 1 |
| Data Bus Width | 16-bit external (32-bit internal registers) |
| Address Bus Width | 24-bit |
| Maximum Addressable Memory | 16 MByte |
| Maximum Clock Frequency | 20 MHz |
| Instruction Set Architecture | CISC, M68000 |
| Operating Mode | Fully static (clock can be stopped) |
| Supply Voltage | 5 V +/- 10% |
| Data Bus Sizing | 8/16/32-bit selectable via S0, S1 |
| Interrupt Levels | 7 autovectored + 1 NMI |
| Package | 64-QFP (14x14 mm, 0.8 mm pitch) |
| Mounting Type | Surface Mount |
MC68SEC000FU20R2 Pin Configuration
| Pin 1 | VCC — 5 V supply |
| Pin 2 | A1 — Address bus bit 1 |
| Pin 3 | A2 — Address bus bit 2 |
| Pin 4 | A3 — Address bus bit 3 |
| Pin 5 | A4 — Address bus bit 4 |
| Pin 6 | A5 — Address bus bit 5 |
| Pin 7 | A6 — Address bus bit 6 |
| Pin 8 | A7 — Address bus bit 7 |
| Pin 9 | A8 — Address bus bit 8 |
| Pin 10 | A9 — Address bus bit 9 |
| Pin 11 | A10 — Address bus bit 10 |
| Pin 12 | A11 — Address bus bit 11 |
| Pin 13 | A12 — Address bus bit 12 |
| Pin 14 | A13 — Address bus bit 13 |
| Pin 15 | A14 — Address bus bit 14 |
| Pin 16 | A15 — Address bus bit 15 |
| Pin 17 | A16 — Address bus bit 16 |
| Pin 18 | A17 — Address bus bit 17 |
| Pin 19 | A18 — Address bus bit 18 |
| Pin 20 | A19 — Address bus bit 19 |
| Pin 21 | VSS — Ground |
| Pin 22 | A20 — Address bus bit 20 |
| Pin 23 | A21 — Address bus bit 21 |
| Pin 24 | A22 — Address bus bit 22 |
| Pin 25 | A23 — Address bus bit 23 |
| Pin 26 | VCC — 5 V supply |
| Pin 27 | FC0 — Function code bit 0 |
| Pin 28 | FC1 — Function code bit 1 |
| Pin 29 | FC2 — Function code bit 2 |
| Pin 30 | AS — Address strobe (active low) |
| Pin 31 | LDS — Lower data strobe (active low) |
| Pin 32 | UDS — Upper data strobe (active low) |
| Pin 33 | R/W — Read/Write (1=read) |
| Pin 34 | VSS — Ground |
| Pin 35 | DTACK — Data transfer acknowledge (active low) |
| Pin 36 | BERR — Bus error (active low) |
| Pin 37 | VCC — 5 V supply |
| Pin 38 | IPL0 — Interrupt request level 0 |
| Pin 39 | IPL1 — Interrupt request level 1 |
| Pin 40 | IPL2 — Interrupt request level 2 |
| Pin 41 | D0 — Data bus bit 0 |
| Pin 42 | D1 — Data bus bit 1 |
| Pin 43 | D2 — Data bus bit 2 |
| Pin 44 | D3 — Data bus bit 3 |
| Pin 45 | D4 — Data bus bit 4 |
| Pin 46 | D5 — Data bus bit 5 |
| Pin 47 | D6 — Data bus bit 6 |
| Pin 48 | D7 — Data bus bit 7 |
| Pin 49 | VSS — Ground |
| Pin 50 | D8 — Data bus bit 8 |
| Pin 51 | D9 — Data bus bit 9 |
| Pin 52 | D10 — Data bus bit 10 |
| Pin 53 | D11 — Data bus bit 11 |
| Pin 54 | D12 — Data bus bit 12 |
| Pin 55 | D13 — Data bus bit 13 |
| Pin 56 | D14 — Data bus bit 14 |
| Pin 57 | D15 — Data bus bit 15 |
| Pin 58 | VCC — 5 V supply |
| Pin 59 | CLK — Clock input (up to 20 MHz) |
| Pin 60 | VSS — Ground |
| Pin 61 | HALT — Halt (active low) |
| Pin 62 | RESET — Reset (active low) |
| Pin 63 | BR — Bus request (active low) |
| Pin 64 | BG — Bus grant (active low) |
Typical Applications
MC68SEC000FU20R2 is suitable for 6 applications: Portable Data-Acquisition Terminal, Handheld Industrial Instrument, Battery-Operated Consumer Product, Legacy Avionics Retrofit Card, Educational 68k Trainer Board, Low-Power Embedded Controller.
Portable Data-Acquisition Terminal
The MC68SEC000FU20R2 fits portable data-acquisition terminals because its fully static 20 MHz M68000 core supports clock-stop idle modes that drop milliwatts between sample bursts. With a 24-bit address bus and 16 MByte addressable memory, it can buffer large logged runs in external SRAM while running legacy 68k acquisition code unchanged. Single 5 V supply simplifies the battery-pack PMIC. Compared with the original MC68000, no -12 V rail is needed, which saves board area and quiescent draw in handheld form factors.
Recommended
Handheld Industrial Instrument
The MC68SEC000FU20R2 is well-suited to handheld industrial instruments where the M68000 instruction set, mature toolchain, and static low-power core let designers reuse decades of legacy firmware. Its 5 V single supply, 64-QFP (14x14 mm) footprint, and seven autovectored interrupt levels cover typical encoder, ADC, and HMI interrupt traffic. The fully static design lets the clock be stopped between user interactions, dropping active power to leakage levels. This combination of footprint, software compatibility, and power behaviour is exactly the niche NXP/Freescale targeted with the SEC000 family.
Recommended
Battery-Operated Consumer Product
The MC68SEC000FU20R2 was explicitly designed for battery-operated consumer products such as PDAs, electronic games, and portable measuring equipment. Its headline feature is the fully static HCMOS core, which lets designers stop the 20 MHz CLK input indefinitely without losing internal state, dropping active power draw to leakage. The 16-bit external data bus, 24-bit address bus, and 5 V single supply keep BOM cost and PMIC complexity low. For cost-sensitive consumer SKUs, the 16 MHz or 10 MHz SEC000 variants in the same 64-QFP footprint can drop in directly to extend battery life.
Recommended
Legacy Avionics Retrofit Card
The MC68SEC000FU20R2 serves avionics retrofit cards where the M68000 instruction set is mandated by long-lifecycle DO-178C certification artefacts. Its 64-QFP (14x14 mm) surface-mount package drops onto existing avionics PCB footprints, and the static core simplifies cold-spare warm-up sequencing at high altitude. The seven interrupt levels plus NMI match the original MC68000 interrupt architecture, allowing legacy RTOS kernels to run unchanged. NXP/Freescale have flagged the part NRND, so retrofit programmes must qualify second-source or buffer stock carefully.
Recommended
Educational 68k Trainer Board
The MC68SEC000FU20R2 is ideal for educational 68k trainer boards used in computer-architecture courses, where students learn the M68000 instruction set, exception model, and bus arbitration. The 20 MHz clock is fast enough to demonstrate interrupt latency and bus-cycle timing on a logic analyser, while the static core lets instructors freeze the clock to walk through pipeline states. The 64-QFP footprint, 5 V supply, and 16-bit external data bus keep lab kit costs low. Drop-in 10 MHz and 16 MHz SEC000 variants let the same PCB support multiple lab exercises.
Recommended
Low-Power Embedded Controller
The MC68SEC000FU20R2 anchors low-power embedded controllers where a 32-bit register model and 16-bit external bus are needed but new Cortex-M firmware is undesirable. Its single 5 V supply eliminates the -12 V rail required by the original MC68000, freeing PCB real estate. Seven autovectored interrupts plus NMI handle motor-control, encoder, and communication stacks, and the 20 MHz performance is sufficient for slow-loop process control. Static core operation lets the controller idle at sub-mW between control ticks, extending battery life in remote or solar-powered installations.
Recommended
Recommended Products Summary
Engineering reference data for MC68SEC000FU20R2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68SEC000FU20 | MC68SEC000FU16 | MC68SEC000FU10 | MC68HC000FU16 | MC68EC000FU20 |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 64-QFP (14x14 mm, 0.8 mm pitch) | 64-QFP (14x14) - same | 64-QFP (14x14) - same | 64-QFP (14x14) - same | 64-QFP (14x14) - same | 64-QFP (14x14) - same |
| Maximum Clock Frequency | 20 MHz | 20 MHz | 16 MHz (-20%) | 10 MHz (-50%) | 16 MHz (-20%) | 20 MHz |
| Core Architecture | 68SEC000 fully static HCMOS | 68SEC000 static HCMOS | 68SEC000 static HCMOS | 68SEC000 static HCMOS | 68HC000 static HCMOS (higher active power) | 68EC000 (less low-power optimised) |
| Supply Voltage | 5 V +/- 10% (single rail) | 5 V single rail | 5 V single rail | 5 V single rail | 5 V single rail | 5 V single rail |
| Data Bus Width | 16-bit external, 32-bit internal | 16/32-bit | 16/32-bit | 16/32-bit | 16/32-bit | 16/32-bit |
| Address Bus Width | 24-bit (16 MByte) | 24-bit (16 MByte) | 24-bit (16 MByte) | 24-bit (16 MByte) | 24-bit (16 MByte) | 24-bit (16 MByte) |
| Interrupt Levels | 7 autovectored + NMI | 7 + NMI | 7 + NMI | 7 + NMI | 7 + NMI | 7 + NMI |
| Fully Static (Clock-Stop) | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Fully static core allows clock-stop with full state retention (vs MC68HC000FU16)
- Single 5 V supply eliminates -12 V rail (vs MC68SEC000FU20 (tube variant))
- 20 MHz throughput at same 64-QFP footprint (vs MC68SEC000FU16)
Design Notes
Estimated: at 20 MHz with all bus lines switching, active current is approximately 50-70 mA from a 5 V rail; leakage in clock-stopped state drops below 1 mA. Place a 100 nF ceramic decoupling capacitor next to each of the four VCC pins (2, 26, 37, 58) and a 10 uF bulk tantalum or ceramic near the supply entry. Avoid daisy-chained VCC traces - star-route from a central decoupling node to minimise supply bounce during bus-arbitration transitions. The original MC68000's -12 V rail is NOT required for the SEC000.
The 64-QFP (14x14 mm) package dissipates roughly 250-350 mW in continuous 20 MHz operation, well within the JEDEC JESD51 theta_JA of around 60-70 C/W for a 4-layer 1 oz board. No external heatsink is required. However, in sealed enclosures above 60 C ambient, verify junction temperature with the manufacturer data sheet thermal table. The plastic thermal pad is not a centre heat-spreader; use a copper pour on the top layer tied to GND for marginal thermal improvement.
Three common pitfalls with the MC68SEC000FU20R2: (1) Do not drive CLK above 20 MHz - AC timing is only guaranteed to 20 MHz; (2) The DTACK signal must be released before the next bus cycle starts to avoid bus-error lockups; (3) The fully static core retains state with CLK stopped, but RESET must be de-asserted cleanly before clocking resumes, or the internal state machine may enter an undefined mode. Always strap FC0-FC2 to known logic levels at reset if supervisor/user mode is fixed by hardware.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status not confirmed in the available NXP product brief; date-code-specific CoC must be requested from the supplier. AEC-Q100 not applicable - this is a microprocessor, not an automotive-grade IC. Conflict-minerals compliance not stated.
