MPC8379EVRAGD - PowerPC e300c4s MPU 400MHz 689-TEPBGA II | NXP
MPN: MPC8379EVRAGD ✓ ActiveMPC8379EVRAGD Overview
A microprocessor (MPU) is the central processing unit of an embedded computer system; the MPC8379EVRAGD sits at the top of the NXP (formerly Freescale) MPC83xx PowerQUICC II Pro family, itself part of the broader Power Architecture / PowerPC ecosystem that influenced modern Power Architecture and ARM-based networking SoCs. MPU performance is governed by clock frequency, cache hierarchy, MMU/virtualization, and integrated peripherals - on all four axes the MPC8379EVRAGD is engineered for deterministic packet processing at wire speed.
Key features include a 400 MHz e300c4s core with integrated single-precision floating-point and dual integer units, 32 KB L1 cache with parity on both instruction and data paths, a dedicated security engine for IPSec, SSL/TLS, and 3DES/AES/SHA acceleration, dual Gigabit Ethernet controllers with MII/RGMII/RTBI/SGMII support, one PCI Express x1 lane, a 32/64-bit DDR1/DDR2 memory controller at up to 400 MHz data rate, four UARTs, two I2C controllers, two SPI controllers, local bus, and dual DMA controllers. The 689-TEPBGA-II package exposes 689 balls on a 1 mm pitch in a 31x31 mm body, with controlled impedance ball-out for high-speed DDR and SerDes signals.
Architecturally, the MPC8379EVRAGD leverages the e300 core built on Power Architecture technology, tightly coupling the CPU to a programmable QUICC Engine datapath for protocol offload (Ethernet, ATM, HDLC, PPP). The internal coherency and snoop logic, combined with a write-back L1 cache, allow sustained throughput for routing, firewalling, and VPN termination workloads. Engineering the system to its limits requires careful DDR2 topology, length-matched address/command traces, solid power-rail decoupling, and thermal relief on the large flip-chip BGA.
Typical applications include secure routers and VPN gateways, industrial automation controllers, networked storage NAS/SAN adapters, factory-floor PLCs and SCADA gateways, point-of-sale terminals, and embedded control planes in aerospace/defense subsystems where extended-temperature screening and long-life silicon are mandatory. When designing with this part, prioritize PCB stack-up selection to maintain 50 ohm single-ended and 100 ohm differential controlled impedance for DDR2 and SGMII; budget ample decoupling near every Vdd ball pair; and follow the NXP hardware reference manual for boot, reset, and JTAG bring-up sequencing.
Drop-in alternatives for MPC8379EVRAGD — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC8379EVRAGD (same form factor and footprint) — differing in Core Architecture, RoHS Status, Security Engine.
MPC8379VVAGD
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MPC8378EVRAGD
✅ Drop-In ⚠️ Specs UnverifiedContact for price
View Datasheet →MPC8377EVRAGD
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MPC8358EVRAGDGA
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8314EVRAGDA
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8379EVRAGD Maximum Ratings & Electrical Characteristics
| Manufacturer | NXP Semiconductors (formerly Freescale) |
| Series | MPC83xx |
| Core Processor | PowerPC e300c4s |
| Core Architecture | Power Architecture (32-bit) |
| Number of Cores | 1 |
| Data Bus Width | 32-bit |
| Maximum Clock Frequency | 400 MHz |
| L1 Cache (I/D) | 32 KB / 32 KB with parity |
| FPU | Yes (single-precision, hardware floating point) |
| Integer Units | Dual |
| Memory Controller | 32/64-bit DDR1/DDR2, up to 400 MHz data rate |
| Ethernet | 2x 10/100/1000 MAC (MII, RMII, RGMII, RTBI, SGMII) |
| PCI Express | 1x PCIe x1 |
| Security Engine | IPSec/SSL/TLS; 3DES, AES, SHA, RNG |
| UART / I2C / SPI | 4 / 2 / 2 |
| Local Bus | Yes (8/16-bit, up to 83 MHz) |
| Operating Temperature | -40C to +125C (V grade - extended) |
| Package | 689-TEPBGA II (31x31 mm, 1.0 mm pitch) |
| RoHS Status | Compliant (lead-free TEPBGA-II) |
| MSL Level | 3 (168 hours, JEDEC J-STD-020) |
MPC8379EVRAGD 689-tepbga ii (31x31 mm, 1.0 mm pitch) Pin Configuration Guide
Pin configuration for MPC8379EVRAGD (689-tepbga ii (31x31 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for MPC8379EVRAGD.
Refer to the datasheet for full pin configuration.
Typical Applications
MPC8379EVRAGD is suitable for 6 applications: Secure VPN / Firewall Gateway, Industrial Automation Controller, Networked Storage (NAS / SAN) Adapter, Secure Point-of-Sale Terminal, Aerospace/Defense Ruggedized SBC, Power-Grid Smart Meter / Substation Controller.
Secure VPN / Firewall Gateway
Engineered around the NXP MPC8379EVRAGD, this secure router design leverages the integrated hardware security engine to accelerate IPSec and SSL/TLS at wire speed, while the dual 10/100/1000 Ethernet controllers with SGMII bring up a WAN port (Copper or Fiber) and a LAN port with no external MAC chip. The 400 MHz e300c4s core handles control-plane routing and CLI management in parallel with the offload engines, and the 32/64-bit DDR2 controller (up to 400 MHz data rate) sustains AES/SHA packet bursts. Compared to a discrete CPU-plus-crypto-chip solution, the MPC8379EVRAGD cuts bill-of-materials by 30% while still achieving 1+ Gbps of VPN throughput on AES-256-GCM and SHA-256 pipelines.
Recommended
Industrial Automation Controller
Inside a PLC or SCADA gateway, the MPC8379EVRAGD's -40C to +125C extended temperature grade supports cabinet installation near motors and switchgear without active cooling. The dual GbE controllers expose separate IP segments for plant-floor and corporate networks, while the four UARTs, two I2C controllers, and two SPI controllers drive RS-485 gateways, sensor hubs, and HMI displays. The QUICC Engine datapath accelerates deterministic EtherCAT and Profinet timers at sub-microsecond jitter, and the hardware floating-point unit computes PID loops for closed-loop machine control at the 400 MHz clock rate.
Recommended
Networked Storage (NAS / SAN) Adapter
For NAS head-units and iSCSI SAN adapters, the MPC8379EVRAGD combines the dual GbE MACs (enabling LACP bonding or separate front-end/back-end networks) with the high-bandwidth DDR2 controller that buffers disk reads and writes between NIC and SATA/SAS bridges. The 400 MHz e300c4s core runs embedded Linux distributions (VxWorks, Linux, or Green Hills INTEGRITY) with hardware crypto acceleration for SMB3 encryption-at-rest workloads. Compared to a software-RC4-only design, the integrated AES engine doubles IOPS while halving CPU load.
Secure Point-of-Sale Terminal
In a PCI PTS-compliant payment terminal, the MPC8379EVRAGD delivers hardware-accelerated 3DES, AES, and SHA functions required for EMV chip authentication and PIN block encryption. The dual Ethernet ports expose a secure LAN connection to the payment processor plus a segregated management port, and the four UARTs interface to the magnetic-stripe reader, smart-card slot, contactless NFC frontend, and thermal printer. The industrial -40C to +125C temperature grade tolerates retail-environment thermal cycling under continuous operation.
Aerospace/Defense Ruggedized SBC
Single-board computers for airborne and ground-vehicle subsystems rely on the MPC8379EVRAGD's -40C to +125C screening, hardware crypto for secure voice/data links, and high shock/vibration tolerance of the under-filled 689-TEPBGA II package. With the e300 core's deterministic interrupt response and the QUICC Engine's protocol offload, the part handles MIL-STD-1553 and ARINC-429 bridge functions alongside Ethernet. Lead-free TEPBGA-II packaging meets aerospace lead-content restrictions where legacy leaded solder reflow is prohibited.
Power-Grid Smart Meter / Substation Controller
Smart meters and substation RTUs use the MPC8379EVRAGD as the central processing element, routing DNP3/IEC 61850 traffic over Ethernet and providing hardware encryption for grid-credential authentication. The hardware floating-point performs real-time power-quality FFT analysis on up to 64 samples per cycle, and the extended -40C to +125C temperature range survives outdoor cabinet conditions. Two Ethernet ports separate the local management network from the utility WAN side, and the rich peripheral set (UART, I2C, SPI, local bus) drives downstream metering ASICs.
Recommended Products Summary
Engineering reference data for MPC8379EVRAGD — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC8379VVAGD | MPC8378EVRAGD | MPC8377EVRAGD | MPC8358EVRAGDGA | MPC8314EVRAGDA |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 689-TEPBGA II (31x31) | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same |
| Core Frequency | 400 MHz | 400 MHz | 300 MHz | 300 MHz | 300 MHz | 266 MHz |
| Core | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300 |
| L1 Cache (I/D) | 32 KB / 32 KB | 32 KB / 32 KB | 32 KB / 32 KB | 32 KB / 32 KB | 32 KB / 32 KB | 16 KB / 16 KB |
| Memory Controller | DDR1/DDR2 32/64-bit, 400 MHz | DDR1/DDR2 32/64-bit, 400 MHz | DDR1/DDR2 32/64-bit, 400 MHz | DDR1/DDR2 32/64-bit, 400 MHz | DDR1/DDR2 32-bit, 400 MHz | DDR1/DDR2 32-bit, 333 MHz |
| Ethernet | 2x 10/100/1000 (RGMII/SGMII) | 2x 10/100/1000 (RGMII/SGMII) | 2x 10/100/1000 (RGMII/SGMII) | 2x 10/100/1000 (RGMII/SGMII) | 1x 10/100/1000 + 1x 10/100 | 1x 10/100/1000 (GMII/TBI) |
| Hardware Security Engine | Yes (IPSec/SSL/TLS, 3DES/AES/SHA/RNG) | Yes (IPSec/SSL/TLS, 3DES/AES/SHA/RNG) | Yes | Limited | Yes | No |
| PCI Express | 1x PCIe x1 | 1x PCIe x1 | 1x PCIe x1 | 1x PCIe x1 | No | No |
| Operating Temperature | -40C to +125C (V-grade) | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | 0C to +105C |
Key Differentiators
- 100 MHz headroom over MPC8377/78 family (vs MPC8378EVRAGD)
- Full hardware security engine vs reduced engine (vs MPC8377EVRAGD)
- Industrial -40C to +125C range vs 0C to +105C (vs MPC8314EVRAGDA)
Design Notes
The 689-TEPBGA II package concentrates 689 balls on a 31x31 mm footprint, leaving a large central die for thermal output. Estimated: at the maximum 400 MHz core clock with both GbE MACs active and the security engine under load, dissipation is in the 5-8 W range; route at least four thermal vias under the die-down balls and use a 4-6 layer PCB with continuous internal ground planes for adequate heat spreading across the -40C to +125C extended temperature range.
The DDR2 controller supports 32- and 64-bit configurations at up to 400 MHz data rate, requiring strict impedance control (50 ohm single-ended for address/command, 100 ohm differential for clock, 50 ohm matched traces per byte group). Length-match all DDR2 signals within 25 mil tolerance, use VTT termination at the byte-group endpoints, and place the controller no more than 6 inches from the DIMM/soldered-down SDRAM to avoid signal-integrity issues.
Route SGMII differential pairs (within the dual GbE MAC) with 100 ohm differential impedance, length-matching to within 5 mil, and keep them isolated from noisy digital paths. Keep the PCIe x1 transmit pair ac-coupled with 75 nF (or 100 nF) capacitors placed close to the source, and follow the standard PCIe CEM routing guidelines for the card-edge connector.
Use a multi-rail sequencing controller to enforce the required NXP MPC8379E power-up sequence: core Vdd before I/O Vdd before DDR2 Vdd, with monotonic rise and tight 1 ms ramp windows. Place 0.1 uF MLCC caps within 100 mil of every power ball, and add bulk tantalum/polymer caps of 100 uF or more on the core rail to absorb transient current spikes from the security engine.
Avoid driving unused PCIe or SGMII lanes during bring-up - configure default pin functions in NXP U-Boot or similar first-stage bootloader before enabling peripherals. Exceeding the -40C to +125C junction range on cold-start may cause DDR2 training failures; provision the system design to monitor on-board temperature via the MPC8379E's internal thermal diode and to gate high-speed I/O during cold-boot sequence.
Compliance Information
Lead-free TEPBGA-II packaging per NXP product data. RoHS compliant. Industrial extended temperature -40C to +125C screening on the V-grade.
