MPC8379EVRAJF - PowerQUICC II Pro e300c4s 533MHz MPU | NXP | TEPBGA-689
MPN: MPC8379EVRAJF ✓ ActiveMPC8379EVRAJF Overview
What is a PowerQUICC II Pro MPU? The PowerQUICC II Pro is the third generation of Freescale/NXP's PowerQUICC communications-processor architecture. It belongs to the MPU/MPSoC product hierarchy (microprocessor unit -> communications processor -> PowerQUICC family -> PowerQUICC II Pro). The e300c4s core implements the PowerPC Book E instruction set with signal-processing (SP) extensions, paired with a system-on-chip peripheral set that includes QUICC Engine communications accelerators, DDR1/DDR2 memory controllers, PCI/PCI-X interfaces, USB 2.0, Gigabit Ethernet MACs, and a hardware security engine for encryption offload.
Key features include a 32-bit PowerPC e300c4s core, 533 MHz maximum core frequency, an integrated security engine (SEC 3.3) supporting DES/3DES/AES/SHA, dual 10/100/1000 Mbit/s Ethernet controllers, DDR1/DDR2 SDRAM controller with ECC, PCI-X 133 MHz local bus, USB 2.0 high-speed host/device, and an integrated QUICC Engine subsystem for HDLC/TDM/ATM serial-channel termination.
The architecture combines an out-of-order-execution-capable integer/branch unit, dual 32 KB L1 instruction and data caches, and a unified 256 KB L2 cache for low-latency instruction and data access. Fabricated in a 130 nm CMOS process, the device is designed for sustained wire-speed packet processing at line rates of OC-12/STM-4 and Gigabit Ethernet, freeing the host CPU from per-packet interrupt overhead.
Typical applications include industrial Ethernet routers and switches, secure broadband gateways, network-attached storage controllers, factory-automation PLCs, and intelligent line-card controllers in legacy telecom switching. The integrated security engine makes it especially attractive for VPN concentrators, IPsec/SSL terminators, and any node that must process encrypted traffic at line rate without host CPU bottlenecks.
When designing with this device, allocate a 4-layer PCB stack-up and provide matched-length impedance control on DDR2 and RGMII traces to maintain signal integrity at 533 MHz. Use the hardware security engine for bulk crypto to keep the e300 core available for control-plane and exception handling tasks.
This page synthesizes distributor stock, NXP PowerQUICC II Pro family data, and drop-in alternative guidance that goes beyond the manufacturer datasheet summary alone.
Drop-in alternatives for MPC8379EVRAJF — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
MPC8379EVRAJFA
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8379EVRANNG
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8379CVRAJF
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8378ECVRAJFA
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8358EVRAGDGA
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8379EVRAJF Maximum Ratings & Electrical Characteristics
| Core Architecture | PowerPC e300c4s (Book E + SP extensions) |
| Series | PowerQUICC II Pro (MPC83xx) |
| Data Bus Width | 32-bit |
| Maximum Core Clock | 533 MHz |
| Cores | 1 |
| Supply Voltage | 1 V (core) |
| Package Type | TEPBGA II (31 x 31 mm), 1 mm pitch |
| Pin Count | 689 |
| Package Height | 2.46 mm |
| Lead Finish | Lead-free (Pb-free) |
| Mounting Type | Surface Mount (BGA) |
| L1 Cache | 32 KB I-cache + 32 KB D-cache |
| L2 Cache | 256 KB unified |
| Security Engine | SEC 3.3 (DES/3DES/AES/SHA) |
| Memory Controller | DDR1/DDR2 SDRAM with ECC |
| Ethernet | Dual 10/100/1000 Mbit/s GMACs (RGMII) |
| Local Bus | PCI / PCI-X 133 MHz |
| USB | USB 2.0 High-Speed Host/Device |
| QUICC Engine | Yes (HDLC/TDM/ATM termination) |
| RoHS Status | Compliant |
| Process Technology | 130 nm CMOS |
MPC8379EVRAJF 2.46 mm Pin Configuration Guide
Pin configuration for MPC8379EVRAJF (2.46 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for MPC8379EVRAJF.
Refer to the datasheet for full pin configuration.
Typical Applications
MPC8379EVRAJF is suitable for 6 applications: Industrial Ethernet Router, Secure Broadband Gateway, Network-Attached Storage (NAS) Controller, Factory Automation PLC, IPsec/SSL VPN Concentrator, Intelligent Line-Card Controller (Telecom).
Industrial Ethernet Router
The MPC8379EVRAJF is purpose-built for managed industrial Ethernet routers that require line-rate packet processing with hardware IPsec acceleration. Its dual Gigabit Ethernet MACs (RGMII) provide two independent GbE uplinks, while the QUICC Engine subsystem terminates HDLC/TDM channels for legacy serial interfaces. The 533 MHz e300c4s core handles routing-table lookups, OSPF/BGP forwarding, and the SEC 3.3 engine accelerates AES-256/SHA-256 IPsec ESP at multi-Gigabit throughput. Compared with a software-only crypto stack on a generic ARM SoC, the MPC8379E leaves the host CPU available for control-plane and routing-protocol tasks. A typical 4-layer PCB layout with 50 ohm controlled-impedance traces on RGMII and DDR2 lines is sufficient for production.
Recommended
Secure Broadband Gateway
Broadband gateway designs benefit from the MPC8379EVRAJF's integrated SEC 3.3 hardware crypto engine, which performs DES/3DES/AES/SHA/RNG operations at line rate without loading the host core. Combined with the DDR1/DDR2 SDRAM controller (with ECC for robust VPN session storage) and the USB 2.0 high-speed host/device port for peripheral or storage expansion, the device forms a complete secure residential/SOHO gateway SoC. The QUICC Engine offloads TDM voice channels in VoIP gateway derivatives. Using the hardware crypto engine rather than a software stack keeps VPN throughput above 800 Mbit/s at typical packet sizes.
Recommended
Network-Attached Storage (NAS) Controller
The MPC8379EVRAJF serves as a NAS controller SoC for SMB/SME storage appliances, integrating a DDR2 controller with ECC (essential for reliable storage) and dual Gigabit Ethernet MACs for link-aggregation or bonded WAN configurations. The PCI-X 133 MHz local bus connects to SAS/SATA RAID controllers, and the USB 2.0 high-speed port supports external backup drives. The e300c4s core running at 533 MHz executes NAS file-system stacks (SMB, NFS, iSCSI) while the QUICC Engine handles tape-backup or inter-shelf I/O. Hardware crypto offload enables encrypted volumes without measurable throughput loss.
Recommended
Factory Automation PLC
Industrial PLCs and factory-automation controllers use the MPC8379EVRAJF as a deterministic real-time processor with extended industrial temperature support (V suffix). The PCI/PCI-X bus connects to modular I/O cards, the QUICC Engine handles fieldbus protocols such as PROFIBUS or CANopen over HDLC/TDM, and the dual GbE MACs enable PROFINET or EtherNet/IP ring topologies. The 130 nm CMOS process and lead-free TEPBGA II package provide long-term reliability in 24/7 factory environments. The integrated security engine secures IP-based machine-to-machine (M2M) traffic on the plant floor.
Recommended
IPsec/SSL VPN Concentrator
Dedicated VPN concentrators leverage the MPC8379EVRAJF's SEC 3.3 engine for bulk AES-256/SHA-256 IPsec ESP and SSL/TLS record processing. The engine delivers multi-Gigabit encrypted throughput while the 533 MHz e300c4s core handles IKE key exchange, session-state management, and the control plane. The dual GbE MACs enable a dedicated WAN-side and LAN-side interface without an external switch. Compared with software-only IPsec stacks, the SEC 3.3 hardware engine typically delivers 5-10x the throughput at the same core clock, making the MPC8379E a strong choice for branch-office VPN aggregation.
Recommended
Intelligent Line-Card Controller (Telecom)
Legacy telecom switching equipment uses the MPC8379EVRAJF as an intelligent line-card controller, with the QUICC Engine terminating T1/E1/J1 and DS-3/E3 framers, the PCI-X bus connecting to framer/serializer ASICs, and the dual GbE MACs providing uplink to the switching fabric. The hardware security engine secures SS7/SIGTRAN signaling if required. The 32 KB I-cache and 32 KB D-cache minimize interrupt latency for per-channel processing, and the 256 KB unified L2 cache accelerates packet-header classification at OC-12/STM-4 line rates.
Recommended
Recommended Products Summary
Engineering reference data for MPC8379EVRAJF — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC8379EVRAJFA | MPC8379EVRANNG | MPC8379CVRAJF | MPC8378ECVRAJFA | MPC8358EVRAGDGA |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 689-TEPBGA II (31x31) | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same | 689-TEPBGA II (31x31) - same |
| Core Architecture | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300c4s | PowerPC e300c3 |
| Security Engine | SEC 3.3 (DES/3DES/AES/SHA) | SEC 3.3 (DES/3DES/AES/SHA) | Disabled (no SEC) | SEC 3.3 (DES/3DES/AES/SHA) | SEC 3.3 | Earlier SEC revision |
| Operating Temperature Grade | Extended Industrial (V suffix) | Extended Industrial (V suffix) | Extended Industrial (V suffix) | Commercial (C suffix) | Commercial (C suffix) | Industrial |
| QUICC Engine Channels | — | Yes (full channelization) | Yes (full channelization) | Yes (full channelization) | Reduced channel count | Reduced channel count |
| Encryption Enabled (E suffix) | Yes | Yes | No (NNG suffix) | Yes | Yes | Yes |
Key Differentiators
- 533 MHz e300c4s core with active SEC 3.3 hardware crypto (vs MPC8379EVRANNG)
- Extended industrial temperature grade (V suffix) (vs MPC8379CVRAJF)
- Latest-generation SEC 3.3 with public-key acceleration (vs MPC8358EVRAGDGA)
Design Notes
The MPC8379EVRAJF's 689-ball TEPBGA II package at 1 mm pitch requires a 4-layer or better PCB stack-up with laser-drilled or mechanically drilled microvias (typical 0.1 mm via-pad, 0.15 mm antipad). Use 50 ohm single-ended controlled impedance for RGMII traces and 100 ohm differential for DDR2 clocks/address/control. Match DDR2 data-group trace lengths within +/- 25 mils and keep address/command traces within +/- 50 mils of the clock per the NXP hardware design guide. Provide at least 1 oz copper on outer layers under the BGA for power/ground thermal spreading.
At 533 MHz core clock with both GbE MACs and the SEC engine active, the MPC8379EVRAJF can dissipate 5-8 W depending on workload. The 689-TEPBGA II package has a typical theta_JA of 12-15 C/W on a JEDEC JESD51 4-layer test board. For industrial enclosure designs without forced airflow, a 25-30 mm square copper-pour heat-spreader directly under the exposed thermal pad, plus 4 thermal vias in the pad array, is recommended to keep junction temperature below 105 C at +85 C ambient.
Place the DDR2 SDRAM chips on the same PCB side as the MPC8379EVRAJF and route the DDR2 bus with matched-length, impedance-controlled traces. Decouple each power rail (VDD_CORE, VDD_DDR, VDD_PCI, VDD_ETH, VDD_USB) with at least one bulk 22 uF tantalum or polymer cap plus 0.1 uF and 1 nF ceramic caps as close as practical to each BGA ball-pair. Provide a clean analog ground island under the QUICC Engine TDM transceivers to minimize crosstalk into adjacent digital returns.
Do not substitute the MPC8379EVRAJF with the non-encrypted MPC8379EVRANNG without re-validating the security-engine firmware boot path - the device tree and U-Boot board configuration must remove SEC driver initialization. Likewise, swapping the industrial-V variant for the commercial-C variant without thermal re-validation can cause junction-temperature failure at +85 C ambient. Always check the NXP MPC8379E errata document before finalizing the PCB layout, particularly for DDR2 timing and QUICC Engine initialization workarounds.
Compliance Information
Lead-free per DigiChip datasheet entry ('LEAD FREE, PLASTIC, BGA-689'). RoHS compliance confirmed by NXP PowerQUICC II Pro family documentation. AEC-Q100 is not applicable to communications processors of this class. Halogen-free status and REACH SVHC declarations should be confirmed with the NXP product environmental compliance data sheet for the specific date code ordered.
