MPC885ZP133 - PowerQUICC 32-Bit 133MHz MPU | NXP | 357-PBGA
MPN: MPC885ZP133 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $28.75 | $287.50 |
| 100 | $24 | $2,400.00 |
| 500 | $19.5 | $9,750.00 |
| 1,000 | $16.25 | $16,250.00 |
MPC885ZP133 Overview
The PowerQUICC device family sits at the intersection of microprocessors (MPU) and microcontrollers (MCU). A PowerQUICC chip combines a PowerPC-class integer core with dedicated communications-engine peripherals (ATM, HDLC, Ethernet, USB, serial interfaces), eliminating the need for a separate media-access controller. Within the broader taxonomy, it is classified as an embedded MPU under Integrated Circuits, with a sibling hierarchy of communications processors -> networking SoCs -> embedded processors -> semiconductors.
Key features include a 32-bit core running at 133 MHz, integrated 10/100 Mbps Fast Ethernet MAC, dual HDLC/ATM supporting channels, USB (full-speed) and multiple serial interfaces, and a 1.9 V core / 3.3 V I/O dual-rail supply scheme. The integrated peripherals offload the CPU from protocol framing tasks, allowing deterministic throughput at line rate. The 357-PBGA plastic-ball-grid-array package exposes a wide parallel external bus for SDRAM and Flash expansions.
Typical applications include small-business routers, ISDN terminal adapters, ADSL/Cable modems, industrial serial-to-Ethernet gateways, and networked control systems. Operating temperature range is 0 °C to 95 °C.
A design consideration: engineers who need determinism under heavy protocol load should review the reference manual's CPM (Communications Processor Module) section because the offload engine, not the core's MIPS, gates most dataplane work.
This page synthesizes datasheet specifications, an analysis of pin-compatible alternatives, and pragmatic design notes not found in NXP's official hardware-specifications document.
Drop-in alternatives for MPC885ZP133 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC885ZP133 (same form factor and footprint) — differing in Core Architecture, Package, Family, Operating Temperature, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MPC885CZP133
✅ Drop-In✓ In Stock
$28.95 / Unit
View Datasheet →MPC880ZP133
✅ Drop-In✓ In Stock
$26.1 / Unit
View Datasheet →MPC875ZP133
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MPC860DPZQ66D
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MPC852T
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MPC885ZP133 Maximum Ratings & Electrical Characteristics
| Manufacturer | NXP Semiconductors (formerly Freescale) |
| Part Family | PowerQUICC - MPC8xx |
| Core Architecture | PowerPC 603e (MPC8xx) 32-bit |
| Maximum Core Frequency | 133 MHz |
| Core Count | 1 |
| Data Bus Width | 32-bit |
| Core Supply Voltage (Vdd) | 1.7 V to 1.9 V |
| I/O Supply Voltage | 3.3 V |
| Operating Temperature Range | 0 °C to 95 °C |
| Package | 357-PBGA (25 mm × 25 mm) |
| Mounting Type | Surface Mount (BGA) |
| On-chip Ethernet | 1 × 10/100 Fast Ethernet MAC |
| On-chip Serial Peripherals | HDLC/ATM channels, USB (full-speed), SCC/SMC |
| External Memory Bus | 32-bit address/data, SDRAM, Flash support |
| RoHS Status | Compliant |
MPC885ZP133 Pin Configuration
| Pin A1 | Vdd — Core supply voltage (1.8 V nominal) |
| Pin B12 | GND — Ground reference |
| Pin C5 | A0 — External address bus bit 0 |
| Pin D20 | D0 — External data bus bit 0 |
| Pin E7 | TCLK — JTAG test clock |
| Pin F14 | TMS — JTAG test mode select |
| Pin G3 | TRST — JTAG test reset |
| Pin H18 | RX_ER — Ethernet receive error |
| Pin J10 | TX_EN — Ethernet transmit enable |
| Pin K22 | RSV — Reserved pin (per datasheet) |
Typical Applications
MPC885ZP133 is suitable for 6 applications: Small-Business Router, ADSL/Cable Modem, Industrial Serial-to-Ethernet Gateway, ISDN Terminal Adapter, Networked Print Server, Embedded Firewall Appliance.
Small-Business Router
The MPC885ZP133 fits small-business routers because its integrated 10/100 Fast Ethernet MAC and dual HDLC/ATM channels eliminate external PHY and framer ICs, reducing BOM cost. The 133 MHz PowerPC core handles routing table lookups and firewall inspection at line rate for typical WAN interfaces up to T1/E1, while the 32-bit external memory bus supports up to 256 MB SDRAM for route tables and packet buffers. Placed on the main router board between the WAN transceiver and the LAN switch, the device offloads framing to the CPM and frees the core for stateful processing.
Recommended
ADSL/Cable Modem
The MPC885ZP133 is suitable for ADSL and cable modem designs because the integrated USB Full-Speed interface and ATM/HDLC channels directly connect to the DSL or cable front-end without external glue logic. Operating at 133 MHz with a 1.8 V core supply keeps dynamic power below 1 W in the typical residential CPE thermal envelope. The on-chip CPM handles ATM SAR (Segmentation And Reassembly) at line rate, leaving the core free to run PPPoE, TCP/IP, and TR-069 management stacks.
Recommended
Industrial Serial-to-Ethernet Gateway
The MPC885ZP133 serves industrial serial-to-Ethernet gateways because the integrated SCC (Serial Communication Controller) channels convert RS-232/RS-485 traffic directly into TCP/IP packets, while the industrial temperature option (separate ordering code) extends the operating range. The 357-PBGA package provides robust mechanical reliability for DIN-rail mounted enclosures, and the dual-rail power scheme simplifies supply design with both 3.3 V and 1.8 V regulators. Modbus, DNP3, and IEC 60870-5-104 protocol stacks run efficiently on the 32-bit integer core.
Recommended
ISDN Terminal Adapter
The MPC885ZP133 is well-matched to ISDN terminal adapters because the integrated HDLC channels and 4-bit serial interface connect directly to ISDN S/T transceivers like the Motorola MC145574. The 133 MHz core has ample headroom for PPP, Multilink-PPP, and IP routing overheads, while the 32-bit memory bus supports simultaneous PPPoE and route-table operations. The legacy 1.7 V to 1.9 V core / 3.3 V I/O scheme remains compatible with the typical ISDN front-end voltage domain.
Recommended
Networked Print Server
The MPC885ZP133 is suitable for office print-server applications because the integrated 10/100 Ethernet MAC and USB Full-Speed interfaces connect to both the network and the printer engine's peripheral port without extra controllers. The 133 MHz PowerPC core runs network printing stacks such as LPR/LPD and IPP at full line rate, while the on-chip CPM offloads TCP/IP framing. The BGA package enables compact designs that fit inside the printer chassis alongside engine-control electronics.
Recommended
Embedded Firewall Appliance
The MPC885ZP133 fits small embedded firewall appliances because the 133 MHz PowerPC core runs open-source firewall stacks such as Netfilter/iptables with stateful inspection for small office deployments, while the on-chip Ethernet MAC eliminates an external PHY controller. The 32-bit external memory bus supports packet buffer memory up to 64 MB, sufficient for typical state-table lookups at 100 Mbps line rate. The CPM offloads packet classification, leaving the core free for policy enforcement.
Recommended
Recommended Products Summary
Engineering reference data for MPC885ZP133 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC885CZP133 | MPC880ZP133 | MPC875ZP133 | MPC860DPZQ66D | MPC852T |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (25x25) |
| Core Frequency | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 66 MHz | 50 MHz |
| On-chip Ethernet | 10/100 MAC | 10/100 MAC | None | 10/100 MAC (subset) | 10/100 MAC | 10/100 MAC |
| Core Supply | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V | 1.7-1.9 V |
| Operating Temperature | 0 to 95 °C | 0 to 95 °C | 0 to 95 °C | 0 to 95 °C | 0 to 95 °C | 0 to 95 °C |
| USB Interface | USB Full-Speed | USB Full-Speed | USB Full-Speed | None | None (legacy) | None |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Integrated 10/100 Ethernet MAC (vs MPC880ZP133)
- USB Full-Speed interface (vs MPC875ZP133)
- 133 MHz speed grade at 1.8 V core (vs MPC860DPZQ66D)
Design Notes
The 357-ball PBGA at 1.27 mm pitch on a 25 mm × 25 mm body requires microvia or via-in-pad PCB technology to route escape traces from inner balls to the inner layers. Standard through-vias consume too much surface area; use HDI stackups with 1-2-1 or 1-2-1-2 microvia structures. Apply a solder-mask-defined (SMD) pad or non-solder-mask-defined (NSMD) pad consistently across the array - NXP's hardware specifications document recommends NSMD for BGA reliability under thermal cycling. Plane layers under the BGA must keep the area clear of signal traces that would split the power/ground return paths.
The 1.7 V to 1.9 V core supply must ramp before or simultaneously with the 3.3 V I/O supply to prevent latch-up. Per NXP's hardware specifications document, monitor PWRON logic and place a reset hold-off timer of at least 100 ms after both rails stabilize. A 1.8 V LDO such as the TPS7A111 or a synchronous buck converter rated for at least 800 mA is appropriate. Decoupling: place 0.1 µF X7R 0402/0201 capacitors directly under each BGA row, with one bulk 10 µF tantalum or ceramic capacitor per supply pin pair on the back side.
Estimated: At full activity (133 MHz core + CPM at line rate) the part dissipates approximately 1.2 W on the 1.8 V rail. With the 357-PBGA's typical theta-JA of 18 C/W on a 4-layer JEDEC test board, the junction rises ~22 C above ambient. Compute Server-class deployments in well-ventilated chassis rarely need a heatsink, but sealed enclosures should add a small aluminum pad bonded to the top of the BGA via thermal interface material. Avoid placing heat sources directly above the BGA since PBGA plastic packages have no top-side heat spreader.
The 32-bit external memory bus (D0-D31, A0-A31) runs at up to 66 MHz on the 133 MHz speed grade and requires source-synchronous clocking. Match all data and address traces within ±25 mil (0.6 mm), use microstrip or stripline geometry with 50 Ω single-ended impedance, and add 22 Ω series damping resistors near the MPC885. Enable the bus-turnaround logic in the UPM (User-Programmable Machine) to avoid contention on the bidirectional lines.
Do not connect a 5 V peripheral directly to the 3.3 V I/O pins; the MPC885ZP133 is not 5 V tolerant. Use a level translator such as the TXS0108E or resistive dividers. Configure the HRESET pin to remain asserted until both the 1.8 V and 3.3 V rails are in regulation, because premature de-assertion can latch the CPM in an undefined state. Finally, program BDM/JTAG header with all five standard pins (TDI, TDO, TMS, TCK, TRST) plus a pull-up on TRST - missing TRST pull-ups are the most common BDM debug failures during board bring-up.
Compliance Information
RoHS compliance per NXP product page. AEC-Q100 not applicable since MPC885ZP133 is not marketed as an automotive-grade MPU. Halogen-free status not explicitly confirmed in web data.
