MPM3682GRE - 18V 10A Step-Down Power Module QFN | MPS
MPN: MPM3682GRE ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.42 | $8.42 |
| 10 | $7.61 | $76.10 |
| 100 | $6.85 | $685.00 |
| 500 | $6.1 | $3,050.00 |
| 1,000 | $5.48 | $5,480.00 |
MPM3682GRE Overview
Background Knowledge: A Point-of-Load (PoL) DC/DC converter is a non-isolated switching regulator placed physically close to the load it powers (typically a processor, ASIC, or FPGA). Within the broader power management hierarchy, a PoL module sits between the intermediate bus converter and the load ICs, providing tight, fast-responding local rails. Fully integrated modules such as the MPM3682GRE differ from discrete buck designs because the high-di/dt power loop (high-side FET, low-side FET, inductor, and input/output bypass capacitance) is contained inside the package, simplifying PCB layout, reducing radiated EMI, and shrinking total solution footprint.
Key features include Constant-On-Time (COT) control for fast transient response, simple loop compensation that requires no external RC network, and a solution that needs as few as two external components (one resistor and one capacitor) to operate. Built-in protections include over-current, over-voltage, under-voltage, and over-temperature shutdown. The 12x12x4 mm QFN package exposes a thermal pad that enables direct PCB heat-sinking through the inner power planes.
Technical depth: COT control uses the output ripple as part of the PWM ramp, eliminating the need for a closed-loop compensation network in most applications. This architecture achieves sub-microsecond transient response compared with classical voltage-mode or current-mode control, and it scales cleanly to multi-phase or stacked configurations when higher currents are required. Internal MOSFETs and the shielded inductor confine the noisy switching node, keeping the module's radiated EMI signature well below that of a comparable discrete buck.
Typical applications include telecom baseband and FPGA core rails, industrial 12 V intermediate-bus POLs, networking switches and routers, server aux rails, and graphics/embedded computing subsystems. The wide 4.5 V-18 V input range covers both 5 V and 12 V intermediate-bus standards, while the 0.65 V-5 V output range supports legacy and modern logic rails from 1.x V cores up to 5 V analog supplies.
When designing with this device, place the single feedback resistor and the optional soft-start capacitor immediately adjacent to the FB and SS pins. The exposed pad must be soldered to a continuous ground copper pour with multiple thermal vias to keep junction temperature within ratings at full 10 A load; derate output current linearly above 65 deg C ambient.
This page synthesizes distributor pricing, application-ready alternatives, and PCB-level design guidance not bundled in the manufacturer datasheet.
Drop-in alternatives for MPM3682GRE — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPM3682GRE (same form factor and footprint) — differing in Input Voltage Range, MSL Level, Output Voltage Range, Package, Switching Frequency.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MPM3682GLE
✅ Drop-In📋 Reference alternative (not in catalog)
MPM3682GRT
✅ Drop-In📋 Reference alternative (not in catalog)
MPM3682GRE-0001
✅ Drop-In📋 Reference alternative (not in catalog)
MPM3620GQV-Z
✅ Drop-In📋 Reference alternative (not in catalog)
LTC3310SIV-1#PBF
✅ Drop-In✓ In Stock
$5.42 / Unit
View Datasheet →LT8640EUDC#TRPBF
✅ Drop-In✓ In Stock
$5.48 / Unit
View Datasheet →MPM3682GRE Maximum Ratings & Electrical Characteristics
| Topology | Synchronous Buck (Step-Down) |
| Function | Non-Isolated PoL Module DC/DC Converter |
| Input Voltage Range | 4.5 V to 18 V (2.5 V to 18 V with 5 V external VCC bias) |
| Output Voltage Range | 0.65 V to 5 V (adjustable) |
| Continuous Output Current | 10 A |
| Switching Frequency | 500 kHz typical |
| Control Method | Constant-On-Time (COT) |
| Number of Outputs | 1 |
| Package | QFN 12x12x4 mm |
| Mounting Type | Surface Mount |
| Dimension | 12.0 mm x 12.0 mm x 4.0 mm |
| Operating Temperature Range | -40 C to +85 C |
| MSL Level | 3 (168 hours) |
| External Components Required | As few as 2 (1 resistor + 1 capacitor) |
| ECCN | EAR99 |
| HTSUS | 8542.39.0001 |
| RoHS Status | Compliant |
| REACH Status | REACH Unaffected |
MPM3682GRE qfn 12x12x4 mm Pin Configuration Guide
Pin configuration for MPM3682GRE (qfn 12x12x4 mm package). This power device features gate, drain, and source terminals. For non-polarized packages, refer to the manufacturer datasheet for exact pin 1 orientation and footprint details. Common applications include power supply design, motor driving, and load switching.
No detailed pinout data available for MPM3682GRE.
Refer to the datasheet for full pin configuration.
Typical Applications
MPM3682GRE is suitable for 6 applications: FPGA/ASIC Core Rail POL, Networking Switch / Router Power, Server / Storage Aux Rail, Industrial 12 V Intermediate Bus POL, Telecom Baseband & RF Digital, Embedded Vision / Edge AI Module.
FPGA/ASIC Core Rail POL
The MPM3682GRE's 10 A continuous output and 0.65 V-5 V adjustable VOUT range directly match the core-rail requirements of mid-range FPGAs (Xilinx Artix-7, Lattice ECP5) and ASICs that demand sub-microsecond transient response during clock gating transitions. COT control keeps the load step overshoot well below 50 mV even when the FPGA toggles from idle to full computation in nanoseconds, which is critical for jitter-sensitive SERDES lanes. Placed adjacent to the device with a 4-layer PCB thermal pour, the 12x12x4 mm QFN footprint delivers 10 A without active cooling. Recommended companion parts: LT8640EUDC#TRPBF (secondary buck), LMZ14203HTZ/NOPB (system input buck), KSZ9031RNXIC-TR (SERDES reference clock partner).
Recommended
Networking Switch / Router Power
The MPM3682GRE's 4.5 V-18 V input directly accepts the 12 V backplane bus of enterprise networking switches, while its 10 A output drives the SoC and packet processor cores that classify and forward traffic. With 500 kHz COT switching, the fundamental stays below the 1 MHz EMI band so 10 Gbps SERDES references remain clean across the chassis. Thermal performance is robust for closed 1U/2U enclosures with 55 C internal ambient. Recommended companion parts: KSZ8895MQXI (5-port switch), L9678PTR (automotive/battery supervisor alternative), LTC3899EFE (multi-output controller for chassis fans).
Recommended
Server / Storage Aux Rail
The MPM3682GRE provides the tightly regulated auxiliary rails (1.0 V, 1.8 V, 3.3 V) that feed SAS controllers, BMC microcontrollers, DDR termination, and NVMe sidecars in server and storage platforms. Its 0.65 V minimum output supports modern 1.0 V core supplies, and the high integration eliminates the discrete inductor's footprint near the BMC's noise-sensitive ADC inputs. Designers value the exposed-pad QFN thermal path when stuffing the module under a heat-spreader lid. Recommended companion parts: LTC2974IUP#PBF (multi-rail supervisor), LM5180NGUR (auxiliary isolated supply), KSZ9031RNXIA (rack-management PHY).
Recommended
Industrial 12 V Intermediate Bus POL
The MPM3682GRE shines in factory-automation PLCs and industrial PCs that distribute a 12 V or 24 V backplane and need multiple local POL rails. Its 18 V maximum input tolerates the worst-case 24 V rectified nominal bus, and the wide operating temperature range of -40 C to +85 C suits cabinet environments. The internal ceramic input/output capacitors are sized for the noise of nearby motor drivers, while COT control rejects the voltage sags created by adjacent solenoid actuation. Recommended companion parts: LT1970IFE (current sense amplifier for bus monitoring), MCP23S17-E/SO (GPIO expander for diagnostics), LMR23630FQDRRRQ1 (aux 5 V buck).
Recommended
Telecom Baseband & RF Digital
The MPM3682GRE supplies the digital baseband processors and DSP cores in 4G/5G small-cell and macro-cell base stations where clean, fast-transient rails are mandatory. The shielded integrated inductor keeps the switching noise well below the LTE/NR band floors, and the 10 A rating covers the peak current during PHY-layer processing bursts. Two external components minimize BOM complexity, which is critical for the long-life, field-serviceable platforms common in telecom. Recommended companion parts: MAX14852GWE+ (digital isolator for control loop), KSZ9031RNXCC (backhaul Ethernet PHY), LTC2358HLX-18#PBF (baseband ADC).
Recommended
Embedded Vision / Edge AI Module
The MPM3682GRE powers AI accelerators, NPU modules, and embedded vision SoCs that swing from milliwatt idle to multi-amp compute loads within microseconds. COT control produces the fast transient response required to keep the SoC's internal PLL and DDR4/DDR5 PHY within spec during inference bursts, while the integrated inductor shrinks the BOM - critical for compact edge-AI carrier boards. The exposed-pad QFN keeps the module within an 80 C junction at 5-7 W typical load. Recommended companion parts: LM34936QPWPRQ1 (wide-Vin primary buck), KSZ9031RNXIA (edge network PHY), LTC3310SIV-1#PBF (secondary load step).
Recommended
Recommended Products Summary
Engineering reference data for MPM3682GRE — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPM3682GLE | MPM3682GRT | MPM3620GQV-Z | LTC3310SIV-1#PBF | LT8640EUDC#TRPBF |
|---|---|---|---|---|---|---|
| Brand | Monolithic Power Systems | Monolithic Power Systems | Monolithic Power Systems | Monolithic Power Systems | Analog Devices | Analog Devices |
| Package | QFN 12x12x4 mm | QFN 12x12x4 mm - same | QFN 12x12x4 mm - same | QFN smaller class | LGA 6.25x4 mm | QFN 3x3 mm class |
| Output Current | 10 A | 10 A | 10 A | 2 A | 10 A | 20 A (IC, not module) |
| Input Voltage Range | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V | 2.25 V to 5.5 V | 3.4 V to 42 V |
| Output Voltage Range | 0.65 V to 5 V | 0.65 V to 5 V | 0.65 V to 5 V | 0.6 V to 5 V | 0.5 V to 1.2 V | 0.97 V to 41 V |
| Switching Frequency | 500 kHz | 500 kHz | 500 kHz | ~500 kHz | 1 MHz | 200 kHz to 3 MHz |
| Control Topology | COT | COT | COT | COT | Silent Switcher | Silent Switcher 2 |
| Module vs IC | Module (integrated L+C) | Module | Module | Module | Module | IC (external L+C required) |
Key Differentiators
- Fully integrated 10 A POL module - inductor and ceramic bank inside QFN (vs LT8640EUDC#TRPBF)
- 10 A continuous output at 18 V input with COT transient response (vs LTC3310SIV-1#PBF)
- Only two external components required for operation (vs MPM3620GQV-Z (same family))
- Wide 4.5 V-18 V direct input (vs LTC3310SIV-1#PBF)
Design Notes
The QFN 12x12x4 mm package relies entirely on the exposed thermal pad for heat removal. At 10 A and a typical 12 V-to-1.0 V conversion, internal dissipation can reach 3-4 W. Estimated: at 3.5 W with theta_JA near 25 C/W on a 4-layer 2 oz PCB, junction temperature rises roughly 88 C above ambient - so a continuous ground copper pour of at least 1 square inch plus a thermal-via array (0.3 mm pitch, 9+ vias) is mandatory. Derate output current above 65 C ambient or use airflow.
Place the single VOUT-setting resistor (R1 from FB to VOUT, R2 from FB to GND) within 5 mm of the FB pin to minimize noise pickup on the high-impedance feedback trace. The optional soft-start capacitor (typically 22-47 nF on SS) must be placed directly at the SS pin. Keep input/output bulk capacitors (if added externally for transient headroom) close to the module's VIN/VOUT landings to avoid hot-loop inductance. Use 2 oz copper on outer layers under the exposed pad to spread heat.
Do not exceed 18 V on VIN - the module has no over-voltage clamping at the input. When biasing VCC with an external 5 V rail, ensure the 5 V supply is stable before VIN rises above 4.5 V to prevent the internal gate-drive LDO from operating outside its specified range. The FB trace should be routed away from the SW node (which is internal but radiates through the package edges) and away from switching inductors in adjacent modules to avoid feedback injection. Avoid sharing the same ground return with high-current digital logic on a single-layer split plane.
Although the high-di/dt loop is internal, the outer copper layers still carry return currents. Use a single solid ground plane on layer 2 directly under the module footprint; stitch vias around the perimeter at 5 mm spacing to suppress edge radiation. Keep digital signal traces (especially >100 MHz SERDES) at least 8 mm away from the module edges to avoid coupling. If placing the module near an RF antenna or antenna feedline, add a via fence between the module and the RF section.
Compliance Information
RoHS compliant and REACH unaffected per GlobalSpec distributor metadata. ECCN EAR99, HTSUS 8542.39.0001. Not AEC-Q100 qualified - choose automotive-grade MPS modules for vehicle applications. MSL Level 3 (168 hours) - JEDEC J-STD-033 handling required after bag opening.
