OPA404SG - Quad 6.4MHz Precision Difet Op Amp | Texas Instruments
MPN: OPA404SG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $62.4 | $62.40 |
| 10 | $58.1 | $581.00 |
| 100 | $53.7 | $5,370.00 |
| 500 | $49.3 | $24,650.00 |
| 1,000 | $44.9 | $44,900.00 |
Drop-in alternatives for OPA404SG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
OPA404AG
β Drop-Inπ Reference alternative (not in catalog)
OPA404KP
β Drop-Inβ In Stock
$23.9 / Unit
View Datasheet βOPA404SG/883B
β Drop-Inπ Reference alternative (not in catalog)
OPA404SG Maximum Ratings & Electrical Characteristics
| Number of Channels | 4 |
| Bandwidth (-3 dB) | 6.4 MHz |
| Slew Rate | 35 V/us |
| Input Offset Voltage (max) | +/-750 uV |
| Input Bias Current (max) | +/-4 pA |
| Settling Time | 0.01% |
| Total Supply Voltage (max) | 36 V |
| Total Supply Voltage (min) | 10 V |
| Supply Type | Dual supply (e.g. +/-5 V to +/-18 V) |
| Architecture | Difet (dielectrically isolated FET), input cascode |
| Pin Configuration | Standard quad op amp pinout |
| Package | 14-CDIP (ceramic dual-in-line) |
| Mounting Type | Through-Hole |
| Terminal Count | 14 |
| Temperature Grade | Military grade (SG suffix) |
| Input Type | FET (JFET) input |
| Manufacturer | Texas Instruments (originally Burr-Brown) |
OPA404SG Pin Configuration
| Pin 1 | 1OUT β Output of amplifier 1 |
| Pin 2 | 1IN- β Inverting input of amplifier 1 |
| Pin 3 | 1IN+ β Non-inverting input of amplifier 1 |
| Pin 4 | V+ β Positive power supply |
| Pin 5 | 2IN+ β Non-inverting input of amplifier 2 |
| Pin 6 | 2IN- β Inverting input of amplifier 2 |
| Pin 7 | 2OUT β Output of amplifier 2 |
| Pin 8 | 3OUT β Output of amplifier 3 |
| Pin 9 | 3IN- β Inverting input of amplifier 3 |
| Pin 10 | 3IN+ β Non-inverting input of amplifier 3 |
| Pin 11 | V- β Negative power supply |
| Pin 12 | 4IN+ β Non-inverting input of amplifier 4 |
| Pin 13 | 4IN- β Inverting input of amplifier 4 |
| Pin 14 | 4OUT β Output of amplifier 4 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
OPA404SG is suitable for 6 applications: High-Speed Data Acquisition Front End, Active Filter Design, Photodiode Transimpedance Amplification, Defense and Aerospace Instrumentation, Precision Integrator and Sample-Hold Circuits, Test and Measurement Equipment.
High-Speed Data Acquisition Front End
The OPA404SG's 6.4 MHz bandwidth and 35 V/us slew rate make it well suited to amplifying sensor signals ahead of ADCs in high-speed data acquisition systems. Four amplifiers per package allow simultaneous conditioning of multiple input channels with tight channel matching, reducing board area and component count. In a typical design, each channel is configured as a non-inverting buffer or gain stage ahead of a multiplexer or successive-approximation ADC. The 0.01% settling specification ensures the amplifier output stabilizes quickly enough for sampling, and the 4 pA max bias current minimizes error with high-impedance sensor sources. Use supply decoupling of 0.1 uF per supply pin close to the package, and keep analog ground returns separate from digital grounds to preserve the precision offset specification.
Recommended
Active Filter Design
Quad op amp packages are natural fits for active filter topologies such as state-variable and biquad filters, which require three to four amplifiers per filter section. The OPA404SG's 6.4 MHz gain-bandwidth and 35 V/us slew rate support filters with cutoff frequencies in the hundreds of kilohertz while maintaining low distortion, far beyond what general-purpose quads like the TL074 can achieve. The Difet input with 4 pA max bias current allows large resistor values (megaohm range) in low-frequency filters without significant offset error, reducing capacitor sizes. When designing, verify the amplifier bandwidth is at least 50 to 100 times the filter cutoff frequency to prevent Q degradation, and place the filter gain stages symmetrically on the PCB to control parasitic coupling between high-impedance nodes.
Recommended
Photodiode Transimpedance Amplification
The OPA404SG's +/-4 pA maximum input bias current, enabled by the Difet dielectrically isolated FET input cascode design, makes each channel an excellent photodiode transimpedance amplifier for optical receivers and light-metering circuits. Low bias current means dark-current errors stay in the picoamp range even with feedback resistors of 1 to 10 megaohm, translating directly to improved sensitivity at low light levels. The 6.4 MHz bandwidth supports megahertz-class optical signal paths, and 35 V/us slew rate prevents slew-induced distortion on fast optical pulses. Stability requires a small feedback capacitor chosen to cancel photodiode capacitance at the summing node; compute Cf from the noise-gain zero formula in the TI datasheet. Reserve one amplifier channel per package for a low-pass reconstruction or comparison stage.
Recommended
Defense and Aerospace Instrumentation
The SG suffix and hermetic 14-CDIP package position the OPA404SG for military-temperature-grade analog instrumentation, avionics signal conditioning, and defense test equipment where plastic packaging is prohibited by program reliability requirements. The hermetic ceramic package eliminates moisture-related leakage paths that degrade FET-input amplifiers in humid environments, and the /883B variant adds full military screening. Each of the four channels provides 6.4 MHz bandwidth, 35 V/us slew rate, and +/-750 uV max offset for high-accuracy analog computation, filtering, and buffering. Designers should observe through-hole assembly constraints of the CDIP, allow adequate standoff for solder inspection, and verify total supply operation within the 10 V to 36 V range per the TI datasheet before release to production.
Recommended
Precision Integrator and Sample-Hold Circuits
Integrators and sample-hold circuits demand ultra-low input bias current because any input current charges the integration or hold capacitor, causing droop. The OPA404SG's 4 pA maximum bias current yields droop rates in the microvolt-per-millisecond range with practical capacitor values, and the 35 V/us slew rate allows fast acquisition transitions. The Difet input cascode also stabilizes bias current over common-mode voltage, an advantage over ordinary JFET amplifiers whose bias current varies strongly with input level. For best results, use low-leakage capacitor dielectrics such as polypropylene or C0G/NP0 ceramic, guard the summing node with a driven shield connected to a follower-buffered ground, and select PTFE or clean FR-4 PCB surfaces to minimize board leakage currents that would otherwise dominate the 4 pA input current.
Recommended
Test and Measurement Equipment
Bench instruments such as oscilloscope front ends, function generators, and data loggers benefit from the OPA404SG's combination of speed and precision across four channels per package. The 6.4 MHz bandwidth and 35 V/us slew rate reproduce fast measurement waveforms, while 0.01% settling supports accurate digitization and the +/-750 uV offset preserves DC measurement accuracy. The standard quad pinout allows instrument designers to upgrade legacy TL074-based signal paths to Difet performance without PCB redesign, a key point stated explicitly in the TI datasheet. The hermetic CDIP through-hole package also suits field-serviceable instruments where through-hole repair is preferred. Apply 0.1 uF ceramic decoupling on both supply pins, and keep high-impedance input traces short and guarded to preserve bias-current performance.
Recommended
Recommended Products Summary
Engineering reference data for OPA404SG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | OPA404AG | OPA404KP | OPA404SG/883B |
|---|---|---|---|---|
| Package | 14-CDIP (through-hole) | 14-DIP (through-hole) | 14-DIP (through-hole) | 14-CDIP (through-hole) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments (Burr-Brown legacy) |
| Bandwidth | 6.4 MHz | 6.4 MHz | 6.4 MHz | 6.4 MHz |
| Slew Rate | 35 V/us | 35 V/us | 35 V/us | 35 V/us |
| Input Offset Voltage (max) | +/-750 uV | +/-750 uV | +/-750 uV | +/-750 uV |
| Input Bias Current (max) | +/-4 pA | +/-4 pA | +/-4 pA | +/-4 pA |
| Total Supply Range | 10 V to 36 V | 10 V to 36 V | 10 V to 36 V | 10 V to 36 V |
| Temperature Grade | Military (SG) | Commercial (AG) | Commercial/Industrial (KP) | Military with MIL-STD-883 screening |
| Screening / Qualification | Standard hermetic CDIP | None (plastic) | None (plastic) | MIL-STD-883 |
Key Differentiators
- Difet input cascode delivers both speed and precision (vs TL074CN)
- Hermetic military-grade CDIP packaging (vs OPA404KP)
- MIL-STD-883 screened variant available (vs OPA404AG)
Design Notes
Use short, direct feedback traces around each amplifier channel; with 6.4 MHz bandwidth, long feedback loops add inductance and parasitic capacitance that cause peaking or oscillation in gains near unity. Keep high-impedance input nodes (summing junctions, photodiode nodes) as small as possible and surround them with guard rings driven at low impedance. Since the CDIP is through-hole, place decoupling capacitors on the component side directly at pins 4 (V+) and 11 (V-), typically 0.1 uF ceramic per pin plus bulk 4.7-10 uF at the supply entry.
In transimpedance and large-feedback-resistor applications, the junction capacitance of the feedback resistor and input trace capacitance create a noise-gain pole that can destabilize the loop. Estimated: with Rf = 1 megaohm and total input capacitance of 10 pF, a feedback capacitor of a few picofarads is typically needed; compute Cf from the datasheet stability criterion (Cf >= sqrt(Cin/(2*pi*Rf*GBW)) approximation). Verify phase margin on the bench with a square-wave test at the expected signal amplitude given the 35 V/us slew limit.
Do not exceed the 36 V maximum total supply (for example, +/-18 V rails); the 10 V total supply minimum also means single 5 V operation is not supported - this is a dual-supply precision part. When substituting plastic-DIP grades (OPA404AG/KP) for the hermetic SG in high-humidity environments, FET input leakage can rise over life; validate leakage under environmental stress before redesign. For defense programs, confirm whether MIL-STD-883 screening is contractually required and specify OPA404SG/883B explicitly rather than standard SG.
Compliance Information
Ceramic military-grade CDIP legacy part; RoHS/REACH status not stated in the provided data. Hermetic ceramic packaging may be exempt from certain RoHS provisions - verify with TI product pages.
