P82B96TD/S900,118 - 400kHz Dual I2C Bus Buffer SOIC-8 | NXP
MPN: P82B96TD-S900118 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.42 | $1.42 |
| 10 | $1.28 | $12.80 |
| 100 | $1.02 | $102.00 |
| 500 | $0.84 | $420.00 |
| 1,000 | $0.71 | $710.00 |
P82B96TD-S900118 Overview
An I2C bus buffer, also called a bus repeater or redriver, is an interface IC that sits between an I2C master and the bus load. Within the interface IC hierarchy (bus buffer -> signal buffer/repeater -> interface IC -> semiconductor), it solves the classic I2C scaling problems: total bus capacitance limits, cable length, and mixed-voltage interconnection. By splitting SCL and SDA into independent forward (Tx/Ty) and reverse (Rx/Ry) signal pairs, the P82B96 electrically isolates two bus segments while remaining fully non-latching, so lock-up conditions common in simpler repeaters are avoided.
Key features include two independent buffer channels handling both SCL and SDA, bidirectional data transfer with a low 5.0 ns propagation delay, and a wide 2 V to 15 V operating supply that lets one side run at 3.3 V or 5 V I2C logic while the other side drives higher-voltage 9 V or 12 V bus lines. Input capacitance is only 7 pF, minimizing loading on the logic-side bus, and supply current is a low 900 uA.
Architecturally, the bipolar process gives the P82B96 robust drive strength and high static noise immunity. The Ty/Ry pins can sink up to 30 mA equivalent bus current on the cable side, enabling long cables and heavily loaded backplanes that a standard open-drain I2C port cannot drive directly. Voltage levels on the Sx/Sy side follow normal I2C-bus logic, independent of VCC.
Typical applications include mixed-voltage I2C level shifting (3.3 V to 12 V), driving I2C over long cables in industrial control, extending SMBus in servers, and isolating bus segments in telecom and consumer boards.
Design tip: connect Tx and Rx pins together when a simple two-way repeater is needed, and keep pull-up resistor values matched to the 400 kHz timing budget. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for P82B96TD-S900118 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
P82B96TD,112
✅ Drop-In✓ In Stock
$3.15 / Unit
View Datasheet →P82B96D
✅ Drop-In📋 Reference alternative (not in catalog)
PCA9600D,112
✅ Drop-In📋 Reference alternative (not in catalog)
P82B96TD-S900118 Specifications
| Function | Dual bidirectional I2C-bus buffer / redriver |
| Channels | 2 (SCL and SDA) |
| Supply Voltage Range | 2 V to 15 V |
| Supply Current | 900 uA |
| Max Data Rate | 400 kHz |
| Propagation Delay | 5.0 ns |
| Input Capacitance | 7 pF |
| Bus Interface Levels | 2.5 V / 3.3 V / 5 V / 9 V / 12 V (up to 15 V logic) |
| Operating Mode | Non-latching, bidirectional |
| Signal Pairs | Sx/Tx/Rx and Sy/Ty/Ry (forward/reverse split) |
| Package | SOIC-8 (SOT96-1, 3.90 mm body) |
| Mounting Type | Surface Mount |
| Technology | Bipolar |
| SMBus Compatibility | 350 uA SMBus interfaces supported |
| Ordering Code Suffix | /S900,118 (Tape & Reel, SOT96-1) |
| RoHS Status | Compliant |
P82B96TD-S900118 Pin Configuration
| Pin 1 | VCC — Supply voltage, 2 V to 15 V |
| Pin 2 | Sx — SCL buffer logic-side I/O (standard I2C levels) |
| Pin 3 | Tx — SCL buffer forward/transmit side I/O (bus side) |
| Pin 4 | GND — Ground |
| Pin 5 | Rx — SCL buffer reverse/receive side I/O (bus side) |
| Pin 6 | Sy — SDA buffer logic-side I/O (standard I2C levels) |
| Pin 7 | Ty — SDA buffer forward/transmit side I/O (bus side) |
| Pin 8 | Ry — SDA buffer reverse/receive side I/O (bus side) |
Typical Applications
P82B96TD-S900118 is suitable for 6 applications: Mixed-Voltage I2C Level Shifting, Long-Cable I2C Bus Extension, SMBus and Server Backplane Interfaces, Industrial Control and PLC I/O Expansion, Consumer Electronics Mixed-Rail Boards, Bus Segmentation and Capacitance Isolation.
Mixed-Voltage I2C Level Shifting
The P82B96's headline application: bridging a 3.3 V or 5 V I2C controller to bus segments running at 9 V, 12 V, or up to 15 V. Because the Sx/Sy logic-side levels follow normal I2C logic independent of the 2 V to 15 V VCC, a 3.3 V MCU can directly drive a 12 V peripheral bus through the buffer without discrete transistor level shifters. The 5.0 ns propagation delay keeps the 400 kHz timing budget intact. Placed between the MCU's SDA/SCL pins and the high-voltage segment with appropriate pull-ups on the T/R side, it adds robustness while consuming only 900 uA. Compared with resistor-divider or MOSFET shifters, it preserves full bidirectional arbitration and clock stretching.
Recommended
Long-Cable I2C Bus Extension
Standard I2C is limited to short traces because of bus capacitance, but the P82B96's bipolar output stage provides strong sink capability on the Ty/Ry side, allowing I2C to run over multi-meter cables in industrial cabinets. The buffer splits each channel into forward (Tx) and reverse (Rx) pins, so the protected Sx side never sees the cable capacitance - the 7 pF input capacitance keeps the master-side load minimal. Use twisted-pair cabling, lower pull-up values (e.g., 220-470 ohm) on the cable side, and a 12 V swing for maximum noise margin, all within the 400 kHz rating. Cascade two P82B96s (Tx/Rx of one to the Sx of the next) for even longer runs.
Recommended
SMBus and Server Backplane Interfaces
The P82B96 is specified to interface with 350 uA SMBus systems, making it well suited to server chassis, IPMB-style backplanes, and power-supply management buses where SMBus devices share long, heavily loaded lines. The buffer isolates the sensitive SMBus segment from low-impedance backplane wiring, and its non-latching bidirectional design avoids the lock-up failure mode that plagues simpler one-directional repeaters when masters arbitrate. With 400 kHz support and 5.0 ns delay, it adds negligible latency to 100 kHz SMBus traffic. Supply current of 900 uA from a 3.3 V or 5 V rail fits standby-power budgets in always-on server platforms.
Recommended
Industrial Control and PLC I/O Expansion
In factory automation and PLC systems, I2C expanders are often mounted on remote boards connected by wiring that exceeds open-drain drive capability. The P82B96 buffers both SCL and SDA (dual channels), so a single SOIC-8 serves a complete I2C port at each segment boundary. Its 2 V to 15 V supply range tolerates industrial rail variation, and the 15 V-rated T/R pins withstand noise transients common in motor-drive cabinets. Designers typically pair it with I/O expanders and keep total capacitance under 400 pF per segment. The bipolar technology's high static noise immunity outperforms CMOS-only repeaters in electrically harsh environments.
Recommended
Consumer Electronics Mixed-Rail Boards
Televisions, set-top boxes, and audio boards frequently mix 3.3 V SoC I2C ports with 5 V, 9 V, or 12 V peripheral domains (tuners, backlight controllers, audio DSPs). The P82B96 bridges these domains in one 8-pin package without discrete translation circuitry. Its non-latching behavior is essential where multiple masters (SoC and an HDMI-CEC-adjacent MCU) arbitrate the same SDA line across the buffer boundary. The 7 pF input capacitance preserves the SoC-side bus budget, while the 12 V-capable side directly connects to higher-rail devices. Low 900 uA consumption supports standby-mode compliance requirements in consumer designs.
Recommended
Bus Segmentation and Capacitance Isolation
When an I2C bus grows beyond the roughly 400 pF capacitance limit - many sensors, EEPROMs, and expanders on one net - the P82B96 partitions it into segments, each segment seeing only its local load. The buffer's forward/reverse split pins allow one-directional segment coupling, useful for isolating noisy or hot-swap sections. Because it is non-latching, back-to-back buffers and looped topologies do not hang the bus. Typical deployment: place one P82B96 per segment boundary, keep each segment under its capacitance budget, and retain 400 kHz operation across the whole tree. The 5.0 ns per-buffer delay means even four cascaded buffers consume under 20 ns.
Recommended
Recommended Products Summary
Engineering reference data for P82B96TD-S900118 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | P82B96TD,112 | P82B96D | PCA9600D,112 |
|---|---|---|---|---|
| Package | SOIC-8 (SOT96-1) | SOIC-8 (SOT96-1) - same | SOIC-8 - same | SOIC-8 - same |
| Brand | NXP Semiconductors | NXP Semiconductors | Texas Instruments | NXP Semiconductors |
| Supply Voltage Range | 2 V to 15 V | 2 V to 15 V | 2 V to 15 V | 4.5 V to 15.5 V |
| Max Bus Speed | 400 kHz | 400 kHz | 400 kHz | 170 kHz |
| Channels | 2 (SCL + SDA) | 2 (SCL + SDA) | 2 (SCL + SDA) | 2 (SCL + SDA) |
| Pin Compatibility | Reference (VCC/Sx/Tx/GND/Rx/Sy/Ty/Ry) | Pin-to-pin identical | Pin-to-pin identical | Similar function, verify pinout before release |
Key Differentiators
- 15 V-rated bus side in a simple SOIC-8 (vs TCA9517DR)
- Non-latching bidirectional architecture (vs PCA9600D,112)
- Dual sourcing supply chain (vs P82B96D (TI))
Design Notes
Do not treat the P82B96 like a TCA9517-style VREF repeater: the Tx and Rx pins are separate forward/reverse signal paths. For a basic two-way repeater, tie Tx to Rx (SCL channel) and Ty to Ry (SDA channel) with short traces. Leaving Rx/Ry floating or mis-wiring them to the logic side is the most common bring-up failure and results in a one-directional, non-arbitrating bus that hangs on multi-master traffic.
Keep the Sx/Sy pull-ups (typically 4.7 kohm to the logic rail, e.g. 3.3 V) close to pins 2 and 6, and place the bus-side pull-ups (220 ohm to 1 kohm depending on cable length and 12 V swing) near pins 3, 5, 7, and 8. Decouple VCC with a 100 nF ceramic capacitor within 5 mm of pin 1 to pin 4. Because the bipolar input stage draws static base current, avoid pull-up values above 10 kohm on the buffered side to preserve noise margin at 400 kHz.
The 2 V to 15 V supply range means VCC can be tied to the logic rail (3.3 V or 5 V) while the T/R side swings to 12 V or 15 V - the Sx/Sy levels are independent of VCC. Estimated power dissipation is negligible: at 900 uA from a 12 V rail the device dissipates about 10.8 mW, so no thermal management is required. Do not exceed 15 V on VCC or the T/R pins; transient suppression (e.g., a 15 V TVS on long cable runs) is prudent in industrial environments.
Compliance Information
RoHS compliance and lead-free finish inferred from the /118 ordering suffix (standard NXP RoHS tape-and-reel pack code) and the active NXP product page status; detailed REACH and halogen data should be confirmed on the NXP product page environmental quality section.
