PIC32MX564F128L-V/BG - 32-bit MCU 128KB Flash USB OTG 121-TFBGA | Microchip
MPN: PIC32MX564F128L-V/BG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.2 | $11.20 |
| 10 | $10.05 | $100.50 |
| 100 | $8.95 | $895.00 |
| 500 | $7.85 | $3,925.00 |
| 1,000 | $6.95 | $6,950.00 |
PIC32MX564F128L-V/BG Overview
A 32-bit microcontroller (MCU) is a programmable integrated circuit that combines a 32-bit processor core, volatile memory (SRAM), non-volatile memory (Flash), and a rich set of peripherals (ADC, timers, communication interfaces, GPIO) in a single chip. PIC32 sits at the intersection of 32-bit performance and 8/16-bit MCU simplicity, making it well suited for bridging traditional embedded designs with higher-throughput applications such as USB, graphics, and connectivity.
Key features of the PIC32MX564F128L-V/BG include integrated USB OTG (Full-Speed), two CAN 2.0b modules, 10-bit ADC with up to 16 channels, a 4-channel DMA controller, 5 timer/counters, two I2C, two SPI, and two UART modules. The device operates from 2.3V to 3.6V with an industrial-grade -40C to +105C temperature range (note: the V/BG variant denotes the V temperature grade of -40C to +105C). It supports up to 85 GPIO pins mapped to the 121-ball TFBGA land pattern.
Architecture-wise, the MIPS32 M4K core implements the MIPS32 Release 2 instruction set with a 5-stage pipeline, hardware multiply/divide, and a prefetch cache that hides Flash latency. The 128 KB Flash and 32 KB SRAM are accessed through a dedicated system bus that feeds the DMA engine, allowing high-bandwidth data movement between peripherals and memory without CPU intervention.
Typical applications include industrial automation controllers, USB human-interface devices (HID), CAN-based automotive networks (body and chassis subsystems), medical instrumentation, and embedded connectivity gateways. The combination of USB OTG, dual CAN, and ADC in one package makes the PIC32MX564F128L-V/BG particularly attractive for industrial nodes that must bridge sensor data to a USB host or CAN bus.
When designing with this part, allocate the 121-ball BGA routing budget early - 0.8 mm pitch requires microvia stack-up and controlled-impedance traces for USB. Decoupling must follow Microchip's recommended 0.1 uF + bulk capacitor placement around each power pin to ensure ADC accuracy and stable USB signaling.
This page synthesizes distributor pricing, drop-in alternatives within the PIC32MX family, and practical BGA layout notes not collected on the manufacturer product page alone.
Drop-in alternatives for PIC32MX564F128L-V/BG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with PIC32MX564F128L-V/BG (same form factor and footprint) — differing in Package, ADC, Timers, Operating Temperature, USB.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
PIC32MX564F128LT-V/BG
✅ Drop-In✓ In Stock
$4.97 / Unit
View Datasheet →PIC32MX564F128L-I/BG
✅ Drop-In✓ In Stock
$5.7 / Unit
View Datasheet →PIC32MX564F064L-V/BG
✅ Drop-In✓ In Stock
$3.74 / Unit
View Datasheet →PIC32MX564F128H-V/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.32 / Unit
View Datasheet →PIC32MX564F128L-V/BG Maximum Ratings & Electrical Characteristics
| Core | MIPS32 M4K |
| CPU Architecture | 32-bit |
| Maximum CPU Speed | 80 MHz |
| Program Flash | 128 KB (128K x 8) |
| SRAM | 32 KB |
| Operating Voltage | 2.3 V to 3.6 V |
| USB Module | USB 2.0 Full-Speed OTG |
| CAN Modules | 2x CAN 2.0b |
| ADC | 10-bit, up to 16 channels |
| DMA Channels | 4 |
| Timers | 5 x 16-bit |
| I2C | 2 modules |
| SPI | 2 modules |
| UART | 2 modules |
| GPIO | 85 I/O pins (max) |
| Package | 121-ball TFBGA, 10x10 mm, 0.8 mm pitch |
| Operating Temperature | -40C to +105C (V grade) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
PIC32MX564F128L-V/BG Pin Configuration
| Pin A1 | VSS — Ground |
| Pin A2 | PGED1/AN0/CN3/RB0 — Programming data / Analog input 0 / RB0 |
| Pin A3 | PGEC1/AN1/CN4/RB1 — Programming clock / Analog input 1 / RB1 |
| Pin A10 | VSS — Ground |
| Pin B1 | VSS — Ground |
| Pin B11 | VSS — Ground |
| Pin C2 | CVREF+/AN9/CN8/RB15 — Comparator Vref+ / Analog input 9 |
| Pin C11 | C1IN-/CVREF-/AN10/CN9/RB14 — Comparator input / Analog input 10 |
| Pin D1 | SDA2/RA2 — I2C2 data / RA2 |
| Pin D11 | AVSS — Analog ground |
| Pin E1 | OSC2/CLKO/RA3 — Oscillator output / RA3 |
| Pin E2 | OSC1/CLKI/RA4 — Oscillator input / RA4 |
| Pin F2 | VDD — Digital power supply 2.3V-3.6V |
| Pin G1 | MCLR — Master clear reset (active low) |
| Pin G11 | AVDD — Analog power supply |
| Pin H1 | RTCC/AN11/CN12/RB12 — RTCC / Analog input 11 |
| Pin J11 | AERFD/AN5/CN7/RB5 — Analog input 5 |
| Pin K1 | VSS — Ground |
| Pin L2 | SOSC1/RC4 — Secondary oscillator input |
| Pin M1 | VDD — Digital power supply |
Typical Applications
PIC32MX564F128L-V/BG is suitable for 7 applications: Industrial USB-CAN Bridge Gateway, USB Human Interface Device (HID), Automotive Body and Chassis CAN Node, Medical Instrumentation Data Logger, Industrial Sensor Aggregator Node, USB-Connected Motor Control Daughter Board, Embedded Connectivity Gateway with Ethernet.
Industrial USB-CAN Bridge Gateway
The PIC32MX564F128L-V/BG is well suited for an industrial USB-to-CAN bridge gateway because it combines USB 2.0 Full-Speed OTG and dual CAN 2.0b controllers on a single die, eliminating an external bridge IC. At 80 MHz the M4K core handles USB device-class firmware plus CANopen or J1939 stack with margin; 128 KB Flash accommodates the combined stack (~70 KB typical) and 32 KB SRAM is sufficient for USB endpoint buffers plus CAN message queues.
Recommended
USB Human Interface Device (HID)
For USB HID peripherals such as industrial keypads, custom control surfaces, and instrumentation knobs, the PIC32MX564F128L-V/BG's USB OTG FS port and 80 MHz MIPS32 M4K core provide enough headroom to run HID-class firmware plus a custom HID report protocol. The 121-ball TFBGA exposes up to 85 I/O pins, enough for matrix-scanned keypads and rotary encoder inputs, while 32 KB SRAM comfortably holds double-buffered HID reports and debounce state.
Recommended
Automotive Body and Chassis CAN Node
The PIC32MX564F128L-V/BG's dual CAN 2.0b controllers enable it to bridge body CAN and chassis CAN buses simultaneously, while the 128 KB Flash and 32 KB SRAM run a CAN node stack with diagnostic UDS handlers. The -40C to +105C V temperature grade covers automotive interior and most under-hood positions; for powertrain or under-harsh underbody locations, a Q100-qualified PIC32 variant would be preferred.
Recommended
Medical Instrumentation Data Logger
The PIC32MX564F128L-V/BG fits medical data loggers that record from multiple sensors and store on removable storage, given its USB device port (to expose the recorded data as a mass-storage device to a host PC) and its 10-bit ADC with up to 16 channels for multi-sensor acquisition. The 128 KB Flash accommodates USB stack plus a small RTOS plus a logger application, while 32 KB SRAM buffers records between flush events. The -40C to +105C temperature grade supports clinical and field environments.
Recommended
Industrial Sensor Aggregator Node
An industrial sensor aggregator node benefits from the PIC32MX564F128L-V/BG's 10-bit ADC with 16 channels and dual CAN interfaces, allowing it to sample multiple analog sensors and forward their readings over CAN to a PLC. The 4-channel DMA moves ADC samples into SRAM without CPU intervention, leaving MIPS32 M4K headroom for filtering and CAN message construction; 128 KB Flash is sufficient for IEC 61131-style libraries plus customer logic.
Recommended
USB-Connected Motor Control Daughter Board
The PIC32MX564F128L-V/BG runs USB host or device plus a PWM motor-control loop, using its 5 timer/counters to generate up to 5 PWM channels and its USB OTG port to expose a command protocol to a host PC. With 128 KB Flash and 32 KB SRAM, it can host USB CDC plus a custom motor-control state machine plus an H-bridge PWM scheme in a single device, reducing BOM cost on educational robotics and small automation platforms.
Recommended
Embedded Connectivity Gateway with Ethernet
Within the PIC32MX5xx family, parts with the integrated Ethernet MAC enable the PIC32MX564F128L-V/BG to act as a low-volume connectivity gateway: USB OTG FS plus optional Ethernet plus dual CAN plus 128 KB Flash cover most lightweight protocol-conversion needs. The MIPS32 M4K core at 80 MHz sustains TCP/IP plus application logic with moderate throughput; 32 KB SRAM requires careful buffering for high-rate packet streams.
Recommended
Recommended Products Summary
Engineering reference data for PIC32MX564F128L-V/BG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PIC32MX564F128LT-V/BG | PIC32MX564F128L-I/BG | PIC32MX564F064L-V/BG | PIC32MX564F128H-V/MR |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 121-ball TFBGA (10x10 mm) | 121-ball TFBGA - same | 121-ball TFBGA - same | 121-ball TFBGA - same | QFN-64 (MR) - different |
| Core / Max Clock | MIPS32 M4K / 80 MHz | MIPS32 M4K / 80 MHz | MIPS32 M4K / 80 MHz | MIPS32 M4K / 80 MHz | MIPS32 M4K / 80 MHz |
| Flash | 128 KB | 128 KB | 128 KB | 64 KB (-50%) | 128 KB |
| SRAM | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| USB OTG | Yes (FS) | Yes (FS) | Yes (FS) | Yes (FS) | Yes (FS) |
| CAN 2.0b | 2 modules | 2 modules | 2 modules | 2 modules | 2 modules |
| Temperature Grade | -40C to +105C (V) | -40C to +105C (V) | -40C to +85C (I) | -40C to +105C (V) | -40C to +105C (V) |
| Operating Voltage | 2.3V to 3.6V | 2.3V to 3.6V | 2.3V to 3.6V | 2.3V to 3.6V | 2.3V to 3.6V |
Key Differentiators
- Higher temperature grade V vs I (vs PIC32MX564F128L-I/BG)
- Twice the Flash of the 064L variant (vs PIC32MX564F064L-V/BG)
- Same silicon as H/MR but BGA package (vs PIC32MX564F128H-V/MR)
Design Notes
The 121-ball TFBGA at 0.8 mm pitch requires a microvia PCB stack-up. Use laser-drilled microvias (4-6 mil pad) for the inner escape rows and a 4-layer stack-up with a continuous ground plane directly under the BGA to control impedance on USB D+/D- traces. Route USB 90 ohm differential pair to within 7 mm of the ball exit. Refer to Microchip's TB3066 USB design checklist for trace geometry.
Place a 0.1 uF decoupling capacitor within 50 mil of every VDD ball, with one bulk 10 uF ceramic per 4 VDD balls. AVDD must be sourced from the same regulator as VDD through an LC filter (10 ohm + 0.1 uF) to keep ADC noise below 1 LSB; otherwise ADC INL degrades by 2-3 LSB. USB bus-power rails need a 4.7 uF tantalum in addition to the ceramics to meet USB inrush during hot-plug.
USB D+/D- (RG2/RG3) require 90 ohm differential impedance with common-mode choke near the connector. The 10-bit ADC shares its sample capacitor with digital I/O - place analog-only pins on a dedicated AVDD rail and avoid switching outputs adjacent to analog traces. Reference Microchip AN3963 for noise-reduction PCB patterns that improve ADC SNR by 3-5 dB in practice.
Avoid configuring both CAN modules and USB OTG simultaneously on the same I/O bank - RG2/RG3 are USB pins and may collide with CAN1 TX/RX if the pin-map is rewritten. Always re-init USB after CAN bit-rate changes, since USB VBUS interrupts can latch and require a manual register clear. Use the PIC32 family errata document (DS80000493) to confirm silicon revision issues.
Compliance Information
RoHS and lead-free per Microchip product page. The PIC32MX family is not AEC-Q100 qualified by default - for automotive customers, request AEC-Q100 variants or use the PIC32MX1xx/2xx automotive-grade sub-family instead.
