SN65LVDS105PWRG4 - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
MPN: SN65LVDS105PWRG4 ✗ End of Life| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
SN65LVDS105PWRG4 Overview
A clock fanout buffer is a timing-distribution component in the clock and timing hierarchy of a digital system. It takes a single reference clock (or data stream) and replicates it to multiple loads while preserving signal integrity, edge rate, and jitter performance. In LVDS-based systems, the fanout buffer also converts single-ended LVTTL levels to low-voltage differential signaling, which offers common-mode noise immunity and lower electromagnetic emissions than single-ended CMOS or TTL clock distribution.
Key features of the SN65LVDS105 include compliance with the ANSI EIA/TIA-644 LVDS electrical standard, typical LVDS output swing of approximately 285 mV into a 100-ohm load, and bus-terminal ESD tolerance that exceeds 12 kV (per TI family datasheet information for this device class). The four LVDS drivers provide deterministic propagation delay with a typical buffer delay of 2.2 ns, enabling predictable multi-load clock skew planning.
The device operates from a 3.3 V nominal supply (3 V to 3.6 V range), making it compatible with standard logic rails. The LVTTL receiver input accepts standard 3.3 V logic levels, so the part can sit directly between an FPGA, MCU, or clock generator output and four separate LVDS destinations such as displays, serializers, or data converters. The SN65LVDS104 companion variant accepts differential input levels (+/-100 mV typical) instead of LVTTL, allowing true LVDS repeater designs.
Typical applications include backplane clock distribution, point-to-point LVDS data links, LCD panel timing distribution, telecom and networking line cards, and industrial control systems requiring 400 Mbps-class differential signaling over controlled-impedance traces.
Design consideration: use 100-ohm differential termination at each LVDS receiver, keep the four output pairs tightly length-matched, and verify supply decoupling with 0.1 uF ceramic capacitors at each VCC pin to minimize jitter contribution.
This page synthesizes distributor listings, cross-reference data, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for SN65LVDS105PWRG4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with SN65LVDS105PWRG4 (same form factor and footprint) — differing in Category, Function, Input Type, Output Type, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
SN65LVDS105PWR
✅ Drop-In✓ In Stock
$1.28 / Unit
View Datasheet →SN65LVDS104PWRG4
✅ Drop-In📋 Reference alternative (not in catalog)
SN65LVDS105PWRG4 Specifications
| Function | 1 LVTTL to 4 LVDS clock fanout buffer / repeater |
| Configuration | 1 x 1:4 Channel |
| Input Type | LVTTL |
| Output Type | LVDS (4 differential pairs) |
| Max Data Rate | 400 Mbps |
| Supply Voltage Range | 3 V to 3.6 V |
| Typical Propagation Delay | 2.2 ns |
| Typical LVDS Output Voltage | 285 mV into 100 ohm load |
| Signaling Standard | ANSI EIA/TIA-644 (LVDS) |
| Bus-Terminal ESD Rating | Exceeds 12 kV |
| Package | TSSOP-16 (PW), 5 mm x 6.4 mm |
| Mounting Type | Surface Mount |
| Packaging | Tape & Reel (PWR suffix) |
| Category | Interface - Signal Buffers, Repeaters, Splitters |
| Lifecycle Status | Discontinued at Digi-Key |
SN65LVDS105PWRG4 tssop-16 (pw), 5 mm x 6.4 mm Pin Configuration Guide
Pin configuration for SN65LVDS105PWRG4 (tssop-16 (pw), 5 mm x 6.4 mm package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for SN65LVDS105PWRG4.
Refer to the datasheet for full pin configuration.
Typical Applications
SN65LVDS105PWRG4 is suitable for 6 applications: Backplane Clock Distribution, LCD Panel Timing Distribution, LVDS Point-to-Point Data Links, Telecom and Networking Line Cards, Industrial Control and Automation, Test and Measurement Instrumentation.
Backplane Clock Distribution
The SN65LVDS105PWRG4 fans a single backplane reference clock from one LVTTL source to four LVDS line cards at up to 400 Mbps. The 2.2 ns typical buffer delay is deterministic across all four outputs, letting the timing engineer budget skew per branch; residual skew is dominated by trace length mismatch, which should be kept under a few millimeters for sub-100 ps skew targets. The approximately 285 mV LVDS swing into 100-ohm loads meets EIA/TIA-644 levels while dissipating minimal power compared with PECL, reducing backplane thermal load. Bus-terminal ESD exceeding 12 kV improves robustness on connectors exposed to card insertion events.
Recommended
LCD Panel Timing Distribution
Display timing generators typically output a single-ended LVTTL pixel or reference clock that must reach multiple receiver chips. The SN65LVDS105PWRG4 converts this LVTTL clock into four LVDS pairs, supplying e.g. source drivers, gate drivers, and a timing controller simultaneously. The low-swing (285 mV) differential signaling produces far lower EMI than single-ended TTL clock routing across flex or ribbon cables - a key consideration for display certification. With 400 Mbps support, the buffer covers high-pixel-rate panels, and its 3-3.6 V supply matches common display logic rails without level shifting.
Recommended
LVDS Point-to-Point Data Links
In high-speed serial links between FPGAs, ASICs, and data converters, the SN65LVDS105PWRG4 serves as a 1-to-4 replicator for clock or control streams at up to 400 Mbps. Because the LVDS outputs comply with ANSI EIA/TIA-644, they drive 100-ohm differential pairs directly, with each output branch terminated at its receiver. The LVTTL input accepts standard 3.3 V FPGA bank levels with no translation circuitry. Compared with replicating via multiple FPGA outputs, the dedicated buffer removes output-to-output skew uncertainty from the FPGA bank specification.
Recommended
Telecom and Networking Line Cards
Line cards distribute a central reference clock to serializers, deserializers, and PHY devices. The SN65LVDS105PWRG4 provides four clean LVDS copies of one LVTTL reference with 2.2 ns typical delay, and the 12 kV-class bus-terminal ESD tolerance adds margin for connectors exposed to field transients. Its 3 V to 3.6 V operation aligns with card logic supplies. Because LVDS is a constant-current, low-swing scheme, switching noise injected into card ground planes is minimal, protecting sensitive RF and analog sections sharing the same board.
Recommended
Industrial Control and Automation
Factory systems such as motion controllers and machine-vision frames distribute encoder and synchronization clocks across several axes. The SN65LVDS105PWRG4 replicates a single LVTTL sync or clock into four LVDS differential pairs rated to 400 Mbps, preserving signal integrity over the 1-5 m cable runs typical inside machinery. Differential signaling provides strong common-mode rejection against motor-drive noise, and the 12 kV-class bus ESD rating withstands harsh industrial environments. The TSSOP-16 surface-mount package supports standard reflow assembly on industrial PCB processes.
Recommended
Test and Measurement Instrumentation
Instrument backplanes (oscilloscope, logic analyzer, signal generator) require jitter-clean clock distribution to multiple acquisition or generation channels. The SN65LVDS105PWRG4 takes one LVTTL reference and delivers four LVDS copies at up to 400 Mbps with a fixed 2.2 ns typical delay, simplifying channel-to-channel phase calibration. LVDS low EMI minimizes radiated noise that could couple into measurement front ends. Designers should decouple each supply pin with 0.1 uF ceramics and route the four output pairs as length-matched 100-ohm differential traces to protect deterministic delay.
Recommended
Recommended Products Summary
Engineering reference data for SN65LVDS105PWRG4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | SN65LVDS105PWR | SN65LVDS104PWRG4 |
|---|---|---|---|
| Package | TSSOP-16 (PW) | TSSOP-16 (PW) - same | TSSOP-16 (PW) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Input Type | LVTTL (single-ended) | LVTTL (single-ended) | Differential (+/-100 mV typical) |
| Output Configuration | 4 x LVDS differential pairs | 4 x LVDS differential pairs | 4 x LVDS differential pairs |
| Max Data Rate | 400 Mbps | 400 Mbps | 400 Mbps |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Signaling Standard | ANSI EIA/TIA-644 LVDS | ANSI EIA/TIA-644 LVDS | ANSI EIA/TIA-644 LVDS |
Key Differentiators
- LVTTL input for direct FPGA/MCU connection (vs SN65LVDS104PWRG4)
- G4 green / tape-and-reel designation for automated assembly (vs SN65LVDS105PWR)
- Four-branch fanout with deterministic delay (vs SN65LVDS104PWRG4)
Design Notes
Route each of the four LVDS output pairs as a controlled 100-ohm differential pair with tight intra-pair length matching, and length-match across the four branches to minimize output-to-output skew beyond the 2.2 ns typical buffer delay. Terminate each pair with 100 ohms at the receiving end, not at the driver. Place the SN65LVDS105PWRG4 close to the LVTTL source to keep the single-ended input stub short, since single-ended traces radiate more than the differential outputs.
Decouple every VCC pin with a 0.1 uF ceramic capacitor placed within 2 mm of the pin, plus one bulk 10 uF capacitor per device. The four simultaneously switching LVDS drivers draw dynamic current at each edge; inadequate decoupling shows up as jitter on all four outputs. The device operates from 3 V to 3.6 V - verify the 3.3 V rail stays in range under load transients, and avoid routing noisy switching-regulator traces near the supply pins.
This part is discontinued at Digi-Key - before new production layouts, confirm lifetime supply or qualify SN65LVDS105PWR as the interchangeable replacement. Do not substitute SN65LVDS104PWRG4 in an LVTTL-source design without checking the input: the 104 expects differential levels (+/-100 mV typical), not single-ended TTL. Also confirm EIA/TIA-644 compliance expectations: the outputs meet the standard, but AC-coupling or cable choices can shift common-mode operating points.
Compliance Information
The G4 suffix traditionally denotes TI's green/RoHS-oriented packaging flow, but explicit RoHS/REACH status was not present in the verified data - confirm on the TI product page quality section.
