FPGA & CPLD
Produtos (6666)
EPM9320LI84-20 - MAX 9000 CPLD, 320 Macro, 60 I/O | Altera
The Altera (now Intel) EPM9320LI84-20 is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in an 84-pin PLCC with J-lead (plastic leaded chip carrier) and rated for the industrial temperature range. It integrates 320 macrocells and provides 60 user I/O pins, with a 20 ns pin-to-pin propagation delay, and is fabricated on the third-generation Multiple Array MatriX (MAX) architecture. The device operates from a 5.0 V supply and supports in-system programmability (ISP) via IEEE Std. 1149.1 JTAG, enabling fast design iteration and field upgrades. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks on a single chip with a programmable interconnect matrix. Within the broader taxonomy, a CPLD sits between small PLDs (PALs, GALs) and FPGAs: it provides fast, deterministic propagation delay (typically 5-20 ns regardless of routing), non-volatile on-chip configuration, and high-drive I/O suitable for bus interfacing and glue-logic replacement. CPLDs are commonly used as address decoders, bus interface bridges, state machines, and configuration controllers in microprocessor and DSP systems. The MAX 9000 family specifically targets high-density glue-logic consolidation, replacing multiple discrete PALs with a single device. Key differentiating features of the EPM9320LI84-20 include its 320-macrocell capacity (the highest density in the MAX 9000 family), 60 user I/Os with 5-V tolerant I/O banks, and an internal operating frequency of up to 118 MHz. The 20 ns tPD is suitable for memory interface glue logic, peripheral controllers, and bus arbitration functions running at up to 50 MHz. The device supports the familiar Altera MAX+PLUS II and Quartus development flows and is pin-compatible with the MAX 9000 LC and GC speed/package variants in the same 84-PLCC pinout, simplifying second-source qualification and lifecycle migration planning. Typical applications include high-density address decoding for 32-bit and 64-bit microprocessor systems, peripheral bus interfacing (PCI, ISA, VME bridges), state-machine controllers for industrial automation, JTAG-based ISP configuration of downstream devices, and legacy logic consolidation where a board was originally implemented with multiple 22V10 or 32-macrocell PALs. The non-volatile EEPROM configuration means the device powers up in a known state without an external boot PROM, simplifying system bring-up. When designing with this part, note that the -20 speed grade is the slowest in the MAX 9000 family; for higher throughput, designers should consider the -15 or -10 variants. The 84-PLCC package requires a socket or careful reflow profiling because of the J-lead thermal mass, and JTAG chain ordering should be planned before PCB layout to avoid contention with other boundary-scan devices. This page synthesizes distributor pricing as of 2026-09-13, pin-compatible MAX 9000 family alternatives from the same 84-PLCC footprint, and practical design notes drawn from the Altera MAX 9000 datasheet family - information not assembled in any single manufacturer document.
EPM9320LI84-20N - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Altera
The Altera EPM9320LI84-20N is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on a 5.0-V CMOS EEPROM process and housed in an 84-pin Plastic Leaded Chip Carrier (PLCC, J-lead) package. It delivers 320 macrocells, 60 user I/O pins, pin-to-pin propagation delays as fast as 10 ns (speed grade -10 family) with a -20 speed grade variant targeting 20 ns, and internal counter frequencies up to 118 MHz. The MAX 9000 architecture integrates 6,000 to 12,000 usable gates in a third-generation Multiple Array MatriX (MAX) fabric and supports 5.0-V in-system programmability through an IEEE 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a programmable interconnect network. Within the broader programmable logic taxonomy, CPLDs sit between simple SPLDs (PALs, GALs, 22V10) and higher-density FPGAs, offering deterministic timing, instant-on operation from on-chip EEPROM, and high fan-in logic that makes them ideal for glue logic, bus decoding, and state-machine implementation. CPLDs are widely used as companion devices to microcontrollers, ASICs, and FPGAs. Key differentiating specifications include 320 macrocells (the largest density in the MAX 9000 family), 60 bidirectional user I/O pins distributed across multiple I/O banks, 16 ns propagation delay in this speed grade, and a 118 MHz internal counter frequency. The non-volatile EEPROM configuration cell eliminates the need for external boot PROM and supports 100+ in-system reprogramming cycles per the MAX 9000 family specification. The MAX 9000 architecture organizes logic into Logic Array Blocks (LABs) connected by a programmable interconnect, with each macrocell containing a programmable AND/OR array and a configurable flip-flop. The EEPROM-based configuration provides instant-on behavior at power-up, making the EPM9320LI84-20N well-suited to deterministic boot sequencing in systems that cannot tolerate FPGA-style configuration latency. Typical applications include address decoding and bus-interface glue logic in microprocessor systems, peripheral controllers for ISA/PCI bus designs, state-machine and sequencer replacement for discrete 22V10 or TTL logic, JTAG boundary-scan integration on legacy boards, and industrial control systems requiring 5-V tolerant I/O. Designers choose MAX 9000 parts specifically when deterministic 10-20 ns timing and instant-on EEPROM behavior outweigh the higher gate counts of modern FPGAs. When designing with this device, treat the PLCC-84 socket footprint as fixed (J-lead, 1.27 mm pitch, 30.35 x 30.35 mm body) and verify that the surrounding PCB layout preserves signal-integrity margins on the JTAG TCK/TMS/TDO/TDI lines. For new designs, consider the MAX II or MAX V families, which offer similar instant-on behavior with lower static power; for legacy board repair, the EPM9320LI84-20N remains a direct footprint-compatible replacement. This page synthesizes distributor pricing from Octopart and DigiKey, drop-in alternative listings, and practical design notes that are not available on the bare manufacturer datasheet, giving engineers an engineer-focused reference for sourcing and replacement decisions on the MAX 9000 family.
EPM9320RC208-10 - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
The Altera EPM9320RC208-10 is a member of the MAX 9000 Complex Programmable Logic Device (CPLD) family, providing 6,000 usable gates and 320 macrocells in a 208-pin RQFP package. According to the verified distributor listings, the device operates from a 5 V supply and is offered in the -10 speed grade, which targets pin-to-pin compatible timing across the family. The part is currently listed by multiple distributors as obsolete/legacy stock, reflecting the maturity of the MAX 9000 series in modern designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EPROM-based programmable logic device that sits between simple PAL/GAL devices and FPGAs in the programmable logic hierarchy. CPLDs typically provide deterministic pin-to-pin propagation delays, instant-on behavior, and a small number of high-drive I/O banks, which makes them ideal for glue logic, bus decoding, state-machine implementation, and power-sequencing control. The MAX 9000 family from Altera (now Intel Programmable Solutions Group) was one of the higher-density CPLD families of its era, extending the MAX architecture with more macrocells and broader I/O counts. Key features of the EPM9320RC208-10 include the 208-pin RQFP package (commercial 'RC' suffix denotes commercial temperature range), the 5 V VCCIO/VCCINT core supply typical of the MAX 9000 family, and 320 macrocells organized into Logic Array Blocks (LABs). The device supports in-system programmability via the Altera ByteBlaster or BitBlaster JTAG interface and is supported by the legacy MAX+PLUS II and Quartus design toolchains. The -10 speed grade defines the worst-case pin-to-pin tPD, which is documented in the MAX 9000 datasheet family. Typical applications for this part include legacy glue-logic replacement, address decoding for 8/16/32-bit microprocessor buses (Intel 80x86, Motorola 68k, MIPS), 5V system bus arbitration, and pin-compatible upgrades for earlier -15 or -20 speed grades where timing margin allows. The non-volatile architecture means the device retains configuration without external boot memory, simplifying board design and reducing BOM cost in industrial control and telecom infrastructure. When designing with the EPM9320RC208-10, engineers should note that the MAX 9000 family is in NRND/last-time-buy status and new designs should target MAX II, MAX V, or MAX 10 families instead. For legacy board repair, the -15 and -20 speed grade variants are pin-compatible upgrades that simply derate timing.
EPM9320RC208-15 - MAX 9000 CPLD 320 Macro Cells 15ns | Altera
The Altera EPM9320RC208-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 320 macro cells, 6,000 usable gates, and a 15 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (Power QFP) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. CPLDs sit between simple PLDs and FPGAs in the programmable logic hierarchy: they offer deterministic, non-volatile timing (EEPROM-based configuration) and instant-on operation, unlike SRAM-based FPGAs that require external configuration memory. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which uses EEPROM cells for configuration storage, giving the device non-volatile operation without a configuration PROM. The EPM9320RC208-15 provides 320 macro cells organized into logic array blocks (LABs), with 6,000 usable gates for implementing glue logic, state machines, bus interfaces, and address decoding. Its 15 ns pin-to-pin delay (speed grade -15) supports system clock rates up to approximately 117.6 MHz for the -15 grade, making it suitable for legacy 5 V TTL/CMOS logic consolidation. The 208-pin RQFP package provides up to 160 user I/O pins, enabling wide bus interfacing in a single device. Typical applications include legacy industrial control boards, telecommunications line cards, bus bridging (PCI, VME, ISA), and replacement of discrete 74-series glue logic. Because the device is EEPROM-based, it retains its configuration after power-down and requires no external configuration device, simplifying board design compared to SRAM FPGAs. When designing with the EPM9320RC208-15, note that it is a 5.0 V core device and is not 3.3 V tolerant on all pins without level shifting. The device was declared obsolete by Altera (now Intel) in 2007 per PDN0706, so new designs should consider the MAX II or MAX V families; however, the EPM9320RC208-15 remains in demand for sustaining existing 5 V designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9320RC208-15N - MAX 9000 CPLD 320 Macro Cells | Intel
The Intel EPM9320RC208-15N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 6,000 usable gates, 320 macro cells, and a 15 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad Flat Pack) package. It operates from a 5.0 V supply and supports a maximum clock frequency of 117.6 MHz. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the architectural flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: CPLD -> programmable logic device -> digital logic IC -> semiconductor. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, using CMOS EEPROM cells for configuration storage, which means the device retains its logic configuration without an external boot PROM. Key features include 320 macro cells organized into 16 logic array blocks, 484 flip-flops, and 128 configurable I/O lines that support both 3.3 V and 5 V operation. The 15 ns propagation delay and 117.6 MHz maximum clock rate make the device suitable for glue logic, bus interfacing, and state-machine implementations that do not require the density of an FPGA. In-system programmability (ISP) is provided through a built-in IEEE Std. 1149.1 JTAG interface, allowing field reconfiguration without removing the device from the board. The MAX 9000 architecture uses a programmable interconnect array to route signals between logic array blocks, giving deterministic timing that simplifies worst-case delay analysis compared with segmented FPGA routing. The EEPROM configuration is non-volatile, so the device is live within microseconds of power-up, an advantage in systems that cannot tolerate the configuration latency of SRAM-based FPGAs. Typical applications include industrial control backplanes, telecommunications line cards, test-and-measurement instrumentation, and legacy system maintenance where the EPM9320 footprint is already qualified. The 5 V tolerant I/O also allows direct interfacing to older TTL logic without level shifters. When designing with this device, verify that the 208-pin RQFP land pattern matches the 0.5 mm terminal pitch and provide adequate decoupling on each VCC pin. Because the part is a mature MAX 9000 device, designers should confirm lifecycle availability before committing to new production. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for replacement and sourcing decisions.
EPM9320RC208-20 - 320-Macrocell MAX 9000 CPLD, 20ns | Altera
The Altera EPM9320RC208-20 is a 320-macrocell, 132-I/O CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 208-pin RQFP (exposed-pad BFQFP) package. Built on Altera's third-generation Multiple Array Matrix (MAX) architecture, it delivers a maximum pin-to-pin propagation delay (tPD) of 20 ns at 5.0 V and integrates approximately 6,000 usable gates with in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. The -20 suffix denotes the 20 ns commercial speed grade. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix, sitting in the programmable logic hierarchy between simple SPLDs/GALs and higher-density FPGAs. CPLDs are favored for glue-logic, bus-interface, state-machine, and power-on control tasks where deterministic timing, fast input-to-output response, and instant-on (zero-config-time) operation are required. The MAX 9000 family extends this concept to higher densities than earlier MAX 5000/7000 generations while retaining the predictable timing that makes CPLDs the preferred choice for asynchronous logic replacement. Key features of the EPM9320RC208-20 include 320 macrocells organized across 20 logic array blocks (LABs), 132 user I/O pins, 5.0 V in-system programmability through the JTAG-compliant IEEE 1149.1 boundary-scan interface, and a commercial 0 °C to 70 °C operating-temperature range. The exposed-pad RQFP-208 package provides a thermal path for moderate dissipation in surface-mount designs, and the EEPROM process allows unlimited reprogramming cycles without an external configuration memory. The device operates from a single 4.75 V to 5.25 V supply, simplifying integration into legacy 5 V logic systems. Architecturally, the MAX 9000 device combines high-density AND-OR PLA-style logic with fast, deterministic interconnect, giving every macrocell a fixed, predictable delay independent of the design's routing complexity. This contrasts sharply with SRAM-based FPGAs, whose interconnect delays vary with placement. The 132 available I/O pins are 5 V-tolerant within the supply range, supporting TTL and CMOS interfacing without level shifters, and each pin is JTAG-controlled for boundary-scan testability. Typical applications for the EPM9320RC208-20 include 5 V glue-logic consolidation in industrial controllers, address decoding and bus-interface bridging in legacy microprocessor systems, peripheral control logic in telecommunications and networking equipment, and state-machine replacement in instrumentation. Its instant-on non-volatile behavior makes it especially suitable for safety-critical boot logic that must be valid before any host processor runs. When designing with this part, observe the 4.75 V to 5.25 V supply window and keep all inputs within the absolute maximum ratings specified in the datasheet; the exposed thermal pad must be soldered to a sufficient copper area to keep junction temperature within the commercial 0 °C to 70 °C range. Use Altera's MAX+PLUS II or Quartus II legacy support tools to fit designs, and verify JTAG chain order when multiple devices share the same boundary-scan port. This page synthesizes distributor pricing, same-package drop-in alternatives, and practical 5 V glue-logic design notes for the EPM9320RC208-20 - information not consolidated in the Altera datasheet alone.
EPM9320RC208-20N - MAX 9000 CPLD 320 Macro Cells 5V | Altera
The Altera EPM9320RC208-20N is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 6,000 usable gates and 320 macro cells with a 20 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad II) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and a programmable interconnect matrix on a single die, allowing designers to implement custom combinational and sequential logic without fabricating an ASIC. Within the logic IC hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: CPLDs offer deterministic, non-volatile timing with instant-on operation, while FPGAs provide higher logic density at the cost of external configuration memory. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture with EEPROM-based configuration. Key features of the EPM9320RC208-20N include 320 macro cells organized into 20 logic array blocks, 6,000 usable gates, a 20 ns maximum pin-to-pin delay (tPD), and a maximum operating frequency of 100 MHz. The device provides 168 user I/O pins in the 208-pin RQFP package and is configured via EEPROM, so it retains its logic configuration without external boot memory. The 5.0 V core and I/O supply simplifies interfacing to legacy 5 V TTL and CMOS logic. The MAX 9000 architecture uses a programmable interconnect array (PIA) to route signals between logic array blocks, giving predictable, fixed timing independent of routing. Each macro cell contains a flip-flop with programmable clock, clock enable, preset, and clear, plus product-term logic for combinatorial functions. This architecture is well suited to glue logic, bus interfacing, and state-machine implementations where deterministic timing matters more than raw gate count. Typical applications include legacy industrial control boards, ISA/VME bus interface logic, address decoding and chip-select generation, and replacement of discrete 74-series glue logic in long-lifecycle systems. The 5 V operation and 20 ns speed grade make it a natural fit for retrofits of existing 5 V designs. When designing with this device, note that the 20 ns speed grade is the slowest of the EPM9320 family; timing-critical paths should be verified against the tPD and tSU/tCO specifications in the manufacturer datasheet. The RQFP-208 package requires careful thermal and signal-integrity layout for the 168 I/O pins. This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for second-sourcing this legacy CPLD.
EPM9320RI208-10N - MAX 9000 CPLD 320 Macro Cells | Altera
The Altera EPM9320RI208-10N is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 6,000 usable gates and 320 macro cells with a 10 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad II) package. It operates from a 5 V supply and supports system clock frequencies up to 100 MHz. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. In the broader hierarchy, a CPLD sits between simple programmable logic devices (SPLDs) and full FPGAs: CPLDs offer deterministic, non-volatile timing and instant-on operation, while FPGAs provide higher logic density. The MAX 9000 family extends the classic MAX 7000 architecture with higher macro cell counts and multiple I/O banks, targeting glue-logic consolidation, bus bridging, and state-machine implementations. The EPM9320RI208-10N provides 320 macro cells organized into 20 logic array blocks (LABs), each containing 16 macro cells. The device supports in-system programmability (ISP) via the JTAG interface, allowing field upgrades without removing the part from the board. Its 10 ns propagation delay and 100 MHz system clock capability make it suitable for high-speed address decoding, DMA arbitration, and peripheral interface logic. The MAX 9000 architecture uses a 5 V core with 5 V-tolerant I/O, ensuring direct compatibility with legacy TTL and CMOS logic levels. The 208-pin RQFP package provides up to 160 user I/O pins, enabling wide bus interfaces without external multiplexing. Non-volatile EEPROM configuration means the device is operational immediately at power-up, eliminating the configuration PROM required by SRAM-based FPGAs. Typical applications include industrial control backplanes, telecommunications line cards, test and measurement instrumentation, and legacy system maintenance where the original design must be preserved. The device is widely used as a drop-in replacement in existing MAX 9000 designs and as a bridge between modern processors and legacy peripherals. When designing with this CPLD, ensure the JTAG chain is properly terminated and that the 5 V supply is well decoupled. Because the part is a mature, non-volatile device, designers should verify availability and consider pin-compatible MAX 9000 variants for long-lifecycle programs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing a single reference for engineers maintaining or sourcing MAX 9000 designs.
EPM9320RI208-20 - MAX 9000 CPLD, 320 Macrocells, 20ns | Intel
The Intel (formerly Altera) EPM9320RI208-20 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, housed in a 208-pin RQFP package with 320 macro cells, 6,000 usable gates, and a 20 ns pin-to-pin propagation delay. The device is built on Altera's third-generation Multiple Array MatriX (MAX) architecture and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantaneously-on programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a programmable interconnect matrix. CPLDs sit hierarchically below FPGAs in the programmable logic taxonomy, offering deterministic timing, lower power, and simpler glue-logic integration than FPGAs, while delivering far higher logic density than legacy SPLDs/PALs. They are commonly used as bus bridges, address decoders, and state-machine controllers in digital systems. Key features of the EPM9320RI208-20 include four dedicated low-skew global input pins (typically used for clocks, clear, and output-enable distribution), a maximum internal operating frequency of 100 MHz, in-system programmability via JTAG, and industrial-grade temperature operation. The 5.0-V VCCIO core supply makes it directly compatible with TTL/CMOS logic families popular in legacy industrial designs. The MAX 9000 architecture employs an enhanced EEPROM process and a fast interconnect matrix to deliver predictable timing across all 320 macro cells. Each Logic Array Block (LAB) contains 16 macro cells feeding the Programmable Interconnect Array (PIA), and the device includes 52 I/O pins in the 208-pin RQFP footprint with multiple I/O standards supported. Typical applications include industrial automation controllers, glue-logic integration in microprocessor designs, bus-interface bridging, address decoding, and state-machine implementation in telecommunications and embedded systems. The non-volatile EEPROM configuration cell ensures instant-on behavior with no external boot PROM required. When designing with this device, ensure that VCC rises monotonically during power-up and that the JTAG pins (TDI, TMS, TCK, TDO) are correctly terminated to support in-system programming. The four dedicated input pins provide low-skew clock distribution across the entire device and should be preferred for global timing signals. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet, enabling faster sourcing decisions for legacy 5-V MAX 9000 designs.
EPM9320RI208-20C - 320-Macrocell MAX 9000 CPLD, 5V, 208-RQFP | Intel
The Intel EPM9320RI208-20C is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 6,000 usable gates, 320 macrocells, and 484 flip-flops in a 208-pin RQFP (Plastic Quad Flat Pack) package. It offers a maximum internal clock frequency of 100 MHz, a pin-to-pin propagation delay (tPD) of 20 ns, and operates from a single 5.0 V supply with 3.3 V or 5.0 V tolerant I/O. According to the MAX 9000 Device Family datasheet, the device is built on third-generation Multiple Array MatriX (MAX) architecture in CMOS EEPROM technology and provides 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines the architectural simplicity and deterministic timing of classic PLDs with the density of small FPGAs. It sits in the broader taxonomy: programmable logic -> CPLD -> MAX 9000 family -> non-volatile logic. CPLDs are commonly used for glue logic, bus interfacing, address decoding, and state-machine control where deterministic propagation delay and instant-on (no boot time) behavior are required. Key features include 320 macrocells with 484 flip-flops, 16 logic array blocks (LABs), a Programmable Interconnect Array (PIA), per-macrocell user-configurable register modes (D, T, JK, SR), and a JTAG-compliant boundary-scan test interface. The device supports industry-standard design entry through Altera's MAX+PLUS II development system with VHDL, Verilog HDL, and AHDL synthesis. The 208-pin RQFP package provides ample I/O for bus-intensive designs and is footprint-compatible with the broader EPM9320 208-pin variants. Architecturally, the MAX 9000 family uses an enhanced EEPROM-based logic element that combines a product-term array with a programmable register, fed into a global interconnect. The PIA routes any LAB output to any other LAB input, providing deterministic, fixed-delay routing independent of logic placement. This guarantees a stable tPD of 20 ns across all logic paths, simplifying timing closure. Typical applications include bus bridge and protocol translation in telecom backplanes, industrial control glue logic with address decoding, peripheral I/O expansion for microcontrollers, JTAG-driven manufacturing test fixtures, and legacy 5V system glue logic where deterministic timing and instant-on boot are required. Industrial temperature grade is supported. When designing with this device, ensure the 5.0 V VCC supply rises monotonically at power-up to avoid EEPROM programming lockouts. Provide adequate decoupling (0.1 uF + bulk) on each VCC pin pair, and respect the JTAG TCK/TMS/TDI/TDO pull-up and pull-down recommendations in the datasheet. This page synthesizes distributor pricing for the EPM9320RI208-20C, pin-compatible drop-in alternatives in the same RQFP-208 footprint, and practical design notes not found in the manufacturer datasheet.
EPM9320RI208-20N - MAX 9000 CPLD 320 Macrocell 208-PQFP | Altera
The Altera EPM9320RI208-20N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 320 macrocells, 484 flip-flops, and a 20 ns pin-to-pin propagation delay, housed in a 208-pin Plastic Quad Flat Pack (PQFP) package with 0.5 mm lead pitch. It is a 5.0 V EEPROM-based programmable logic device offering in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks with a programmable interconnect matrix, allowing designers to implement custom digital logic functions without fabricating an ASIC. Within the programmable logic hierarchy, the CPLD sits between simple PLDs (PAL/GAL) and full FPGAs, offering non-volatile configuration, deterministic timing, and instant-on operation. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which uses EEPROM cells to retain configuration without an external boot device. Key features of the EPM9320RI208-20N include 320 macrocells organized into Logic Array Blocks (LABs), 484 flip-flops, 5.0 V in-system programmability via JTAG, and four dedicated low-skew global input pins typically used for clock, clear, and output-enable distribution. The device supports 3.3 V or 5 V configurable I/O operation, making it suitable for mixed-voltage legacy systems. The industrial temperature grade (I suffix) covers -40C to +85C operation. The MAX 9000 architecture routes signals through a programmable interconnect array that provides predictable, fixed pin-to-pin delays of 20 ns, eliminating the timing uncertainty found in SRAM-based FPGAs. This deterministic timing is critical for glue-logic replacement, bus interface, and state-machine applications where worst-case delay must be guaranteed. Typical applications include legacy system glue logic, ISA/PCI bus interfaces, industrial control state machines, instrumentation front-end logic, and replacement of discrete 74-series logic. The 208-pin PQFP package provides up to 160 user I/O pins for wide bus interfaces. When designing with this device, note that VCC must rise monotonically during power-up, and inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. The EPM9320RI208-20N is a mature, widely second-sourced part; verify lifecycle status before committing to new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for replacement and design-in decisions.
EPM9400LC84-15 - MAX 9000 CPLD 8K Gates 400 Macros | Altera
The Altera EPM9400LC84-15 is a high-density, in-system programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 8,000 usable gates, 400 macro cells, and a maximum operating frequency of 117.6 MHz in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. The "-15" speed grade denotes the 15 ns pin-to-pin logic delay tier, balancing propagation delay and toggle performance for glue-logic and bus-interface applications. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like logic blocks with a central interconnect matrix, sitting in the broader programmable logic hierarchy: CPLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. Unlike SRAM-based FPGAs, MAX 9000 devices store their configuration in on-chip EEPROM, providing instant-on behavior without external boot memory and making them well suited for deterministic boot-critical applications. Key features include 25 logic array blocks, 59 maximum user I/Os, 5.0 V VCCINT core supply with TTL-compatible input thresholds that are also 3.3 V tolerant, and a commercial 0C to 70C operating temperature range. The device is fabricated on a 0.35 um EEPROM process that retains configuration for at least 20 years and supports in-system programmability via the JTAG-compliant IEEE Std. 1149.1 boundary-scan interface. The PLCC-84 package offers a JEDEC-standard through-hole-style leaded footprint that simplifies prototyping and rework. Architecturally, the MAX 9000 family uses a programmable interconnect array (PIA) that routes signals between LABs (Logic Array Blocks), each containing 16 macro cells with shared product-term expanders and I/O control blocks. The EPM9400LC84-15 supports per-pin slew-rate control, programmable ground pins, and JTAG-based in-system programming through dedicated JTAG pins, eliminating the need for a separate EPROM programmer. Typical applications include bus-interface bridging, address decoding and glue logic for microprocessor systems, peripheral controllers (UART, FIFO, memory controllers), industrial control sequencing, and legacy 5V system replacement of discrete TTL/CMOS logic. The deterministic timing of the EEPROM-based architecture also makes it suitable for safety-critical or hard-real-time control where SRAM-FPGA configuration latency is unacceptable. When designing with this device, ensure VCC rises monotonically during power-up and that all four dedicated input pins stay above -0.3 V DC. The 5 V VCCINT rail must remain stable; designers should place decoupling capacitors close to every VCC pin and observe the maximum I/O undershoot/overshoot limits stated in the Operating Requirements for Altera Devices Data Sheet. This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes not assembled on any single manufacturer or distributor datasheet page.
EPM9400LC84-20 - MAX 9000 CPLD 400 Macrocells 5V ISP | Altera
The Altera EPM9400LC84-20 is a high-performance, CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 400 macrocells and approximately 8,000 usable gates in an 84-pin PLCC package. It is built on Altera's third-generation Multiple Array Matrix (MAX) architecture and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. The device achieves pin-to-pin propagation delays as fast as 10 ns (commercial, speed grade -20) and counter frequencies up to 144 MHz, with a maximum user I/O count of 55 lines configurable for 3.3 V or 5 V operation. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays with a programmable interconnect matrix, providing deterministic timing, instant-on operation, and high fan-in for glue-logic, state-machine, and bus-interface functions. CPLDs sit below FPGAs in the programmable logic hierarchy - offering less logic capacity but faster, more predictable timing - and are commonly used as interface bridges, address decoders, and peripheral controllers. The MAX 9000 family extends the classic MAX 7000 architecture with higher density and additional JTAG features. Key features include 400 macrocells, 580 flip-flops, approximately 8,000 usable gates (6,000-12,000 typical range), and 4 LABs (Logic Array Blocks) interconnected by the programmable interconnect matrix. The 84-pin PLCC (Plastic Leaded Chip Carrier) package provides a proven, robust surface-mount footprint long supported by industrial through-hole and socket-mount tooling. The EPM9400LC84-20 utilizes Altera's third-generation MAX architecture with EEPROM configuration memory, meaning the device retains its logic configuration without external configuration memory and powers up instantly to a functional state. This makes it especially well suited for deterministic boot-time applications where FPGAs would require external PROM or longer configuration times. Typical applications include peripheral bus interfacing (PCI, ISA, VME), address decoding and glue logic, state-machine controllers, peripheral drivers (UART, FIFO, timer blocks), and industrial control logic. The 5 V tolerance and JTAG ISP make it convenient for legacy system upgrades and field-reprogrammable embedded designs. When designing with this device, allocate sufficient decoupling capacitance near the VCCINT/VCCIO pins and route JTAG TMS/TCK/TDO/TDI to a 4-pin header for in-system programming. Note that MAX 9000 is an older legacy family; long-term supply may be constrained - check current distributor stock and consider MAX II or MAX V as modern replacements for new designs. This page synthesizes distributor pricing, same-brand MAX 9000 alternatives, and practical design considerations that are not available from any single manufacturer datasheet or distributor listing.
EPM9400RC208-20 - MAX 9000 CPLD 400 Macro Cells 20ns | Altera
The Altera EPM9400RC208-20 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 400 macro cells, 8,000 usable gates, and a 20 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic blocks and a programmable interconnect matrix on a single die, allowing designers to implement custom digital logic without fabricating an ASIC. Within the semiconductor taxonomy, the CPLD sits alongside the FPGA under programmable logic devices (PLDs), which in turn belong to the broader digital integrated circuit family. The MAX 9000 architecture uses a third-generation Multiple Array MatriX (MAX) structure with EEPROM-based configuration, meaning the device retains its programmed logic after power-down without an external configuration memory. The EPM9400RC208-20 delivers 400 macro cells organized into logic array blocks, with 8,000 usable gates for glue logic, state machines, bus interfaces, and address decoding. Its 20 ns pin-to-pin delay supports system clock rates up to 100 MHz, and the 5.0 V core allows direct interfacing with legacy TTL and CMOS logic without level shifters. The EEPROM configuration technology provides non-volatile operation, eliminating the boot-time configuration latency found in SRAM-based FPGAs. Typical applications include legacy industrial control boards, telecommunications line cards, test and measurement instruments, and military/aerospace systems where 5 V logic compatibility and long-term availability are required. The 208-pin RQFP package provides up to 164 user I/O pins, enabling wide bus interfaces and multi-device glue logic consolidation. When designing with this device, ensure the 5.0 V supply is well decoupled and that the JTAG chain is properly terminated for reliable in-system programming. Because the MAX 9000 family is a mature, legacy architecture, designers should verify current availability and consider migration paths to modern CPLD families for new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for evaluation and procurement of the EPM9400RC208-20.
EPM9400RC240-15 - 400-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Intel
The Intel (formerly Altera) EPM9400RC240-15 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, providing 400 macrocells in a 240-pin RQFP (plastic quad flat pack) package with a 15 ns pin-to-pin propagation delay. The device operates at 5.0 V and supports in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, enabling board-level reconfiguration without removing the part. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like logic blocks with a central interconnect matrix, providing deterministic, fast combinatorial and registered logic with predictable timing. Within the broader taxonomy, the EPM9400 sits in the MAX 9000 family, which is itself part of the Programmable Logic Device (PLD) hierarchy under the broader category of programmable logic semiconductors - bridging the gap between discrete 74-series logic and FPGA-class devices. Key features of the EPM9400RC240-15 include 8,000 usable gates, 400 macrocells, a maximum operating frequency of approximately 117.6 MHz, and 5.0 V in-system programmability via JTAG. The MAX 9000 architecture uses Altera's third-generation Multiple Array MatriX (MAX) interconnect, providing fast, deterministic delays across all I/O paths regardless of logic placement. The 15 ns speed grade is the middle of the MAX 9400 family - faster than -20 speed grade parts (20 ns) and slower than -10 grade. The 240-pin RQFP package provides a high pin count for I/O-intensive glue-logic applications, while the EEPROM process technology ensures non-volatile configuration that retains state across power cycles without external boot memory. Typical applications include bus decoding and address mapping in industrial control systems, glue logic between microprocessors and peripherals, I/O expansion in legacy 5 V designs, and state-machine replacement in telecom backplane interfaces. The 5 V tolerance makes it ideal for legacy TTL interfaces that remain common in factory automation and instrumentation. When designing with this part, verify that the I/O bank voltages match the system logic levels - the MAX 9000 family is optimized for 5 V rails and is not directly drop-in compatible with 3.3 V-only logic without level translation. Confirm JTAG chain order and TMS/TCK/TDO/TDI termination when chaining multiple ISP devices. This page synthesizes distributor pricing and stock, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9400RC240-20 - 400 MC, 20 ns MAX 9000 CPLD, 240-RQFP | Altera
The Altera EPM9400RC240-20 is a 400-macrocell (MC), 20 ns pin-to-pin delay member of the MAX 9000 family of high-performance CMOS EEPROM-based Complex Programmable Logic Devices (CPLDs), housed in a 240-pin RQFP (32x32 mm) package with exposed thermal pad. It operates from a single 4.75 V to 5.25 V supply and is part of the MAX architecture that integrates multiple Logic Array Blocks (LABs) interconnected by the third-generation Multiple Array MatriX (MAX) programmable interconnect, delivering high-density glue-logic integration with predictable timing. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the deterministic timing of PAL/PLA architecture with the integration scale of a small FPGA, making it ideal for address decoding, bus interface, state-machine, and control-logic functions. Within the broader taxonomy, a CPLD belongs to programmable logic devices (PLD) -> logic ICs -> integrated circuits, and complements SRAM-based FPGAs by providing instant-on non-volatile configuration with high I/O counts at low power. Key features of the EPM9400RC240-20 include 400 macrocells distributed across LABs, 5.0-V in-system programmability (ISP) via a built-in IEEE Std. 1149.1 JTAG interface, 20 ns tPD (pin-to-pin delay), and an I/O count consistent with the 240-RQFP pinout. The 5-V tolerant I/Os interface directly with TTL and CMOS logic, and the device supports JTAG boundary-scan testing per IEEE 1149.1 for board-level testability. Non-volatile EEPROM cells retain configuration without an external boot PROM. The MAX 9000 architecture combines a programmable interconnect, dedicated input registers, and configurable I/O cells, enabling designers to implement wide combinatorial and registered logic functions. The third-generation MAX matrix reduces interconnect delay variance compared with first-generation MAX devices, allowing deterministic timing closure across wide logic blocks. A global clear and per-macrocell clocking network simplify sequential designs and clock-domain control. Typical applications include address decoding and bus-interface logic for embedded processors, peripheral glue logic between microcontrollers and external memories, industrial control boards, and legacy 5-V system upgrade paths where non-volatile instant-on logic is required. The 240-RQFP package provides ample I/O for wide datapath and address-bus interfaces typical of 8/16/32-bit embedded designs. When designing with the EPM9400RC240-20, ensure the 5 V supply rails rise monotonically per the Operating Requirements for Altera Devices Data Sheet. Inputs may undershoot to -2.0 V or overshoot to 7.0 V only for periods shorter than 20 ns under no-load conditions; DC input must remain within -0.5 V on I/O pins and -0.3 V on the four dedicated input pins. A JTAG chain must observe TCK/TMS/TDO/TDI ordering if multiple 1149.1 devices are present. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 9000 family, and practical design notes that go beyond the manufacturer datasheet, including JTAG programming guidance and supply-rail monotonicity requirements for robust in-system programming.
EPM9480RC208-15 - 480 Macro Cell MAX 9000 CPLD, 15ns | Intel
The Intel EPM9480RC208-15 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 480 macro cells and 10,000 usable gates in a 208-pin RQFP package with a 15 ns pin-to-pin delay. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, it provides 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface and operates at a maximum internal frequency of 117.6 MHz. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that sits between simple SPLDs/glue logic and larger FPGAs. The MAX 9000 family combines multiple Logic Array Blocks (LABs) interconnected by a programmable interconnect array (PIA). Each macro cell contains a programmable AND/OR array and a configurable flip-flop, giving the device deterministic timing with predictable propagation delays—essential for glue logic, bus decoding, and state-machine replacement. Key features include 153 user I/O pins, 5V-tolerant inputs and outputs (with 3.3V PCI-compliant option on selected variants), in-system programmability via JTAG, and a -40C to +85C commercial operating temperature range. The RQFP-208 package has a low-thermal-resistance design suitable for industrial control systems and legacy telecommunications backplane applications. The MAX 9000 architecture uses EEPROM configuration cells, retaining the programmed logic through power cycles without external boot memory. The PIA provides predictable interconnect timing; every signal path traverses the same matrix regardless of placement, simplifying static-timing closure compared to FPGAs. The 15 ns speed grade supports clock rates up to 117.6 MHz on internal logic. Typical applications include legacy industrial control boards, telecommunications line cards, PCI bus interface glue logic, and replacement of discrete 74-series logic. The 5V I/O compatibility makes it suitable for interfacing directly with TTL/CMOS logic in legacy designs. When designing with this part, ensure the JTAG chain conforms to IEEE 1149.1 specifications and that the 5V supply rail has adequate decoupling within 0.5 inches of each VCC pin to maintain signal integrity during in-system programming operations. This page synthesizes distributor pricing, parametric drop-in alternatives, and practical design notes not found in the original datasheet alone.
EPM9480RC208-15N - MAX 9000 CPLD 480 Macro Cells | Altera
The Altera EPM9480RC208-15N is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 10,000 usable gates, 480 macro cells, and a maximum operating frequency of 117.6 MHz, housed in a 208-pin RQFP (PowerQuad Flat Pack) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks with a programmable interconnect matrix, allowing designers to implement custom digital logic functions without fabricating a custom ASIC. CPLDs sit between simple PLDs (PAL/GAL) and FPGAs in the programmable logic hierarchy, offering deterministic timing, non-volatile configuration, and instant-on operation. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which uses EEPROM-based configuration cells for non-volatile operation. Key features of the EPM9480RC208-15N include 480 macro cells organized into logic array blocks, 10,000 usable gates, a 15 ns pin-to-pin propagation delay (speed grade -15), and 117.6 MHz maximum internal frequency. The device provides 5.0 V in-system programmability via the JTAG interface, allowing field upgrades without removing the device from the board. The 208-pin RQFP package offers a high I/O count suitable for bus-intensive designs. The MAX 9000 architecture uses a programmable interconnect array (PIA) to route signals between logic array blocks, providing predictable timing independent of routing. Each macro cell contains a flip-flop and combinatorial logic, enabling both registered and combinatorial functions. The EEPROM configuration retains the design after power-down, eliminating the need for external configuration memory. Typical applications include glue logic consolidation, bus interface bridging, address decoding, state machine implementation, and legacy system maintenance. The 5.0 V operation makes it compatible with older TTL and CMOS logic families, simplifying integration into existing 5 V designs. When designing with this device, ensure the JTAG chain is properly terminated and that the ISP programming voltage is stable. The 208-pin RQFP package requires careful PCB layout to manage signal integrity on high-speed buses. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for evaluation and sourcing.
EPM9480RC208-20 - MAX 9000 CPLD, 12K Gates, 560 Macro Cells | Intel
The Intel (formerly Altera) EPM9480RC208-20 is a high-density Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 12,000 usable gates and 560 macro cells with a 20 ns pin-to-pin propagation delay in a 208-pin RQFP (Plastic Quad Flat Pack) surface-mount package. It is built on a 5V CMOS EEPROM-based architecture that provides non-volatile, in-system programmable logic with 100 percent factory-tested AC and DC characteristics. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL devices and high-density FPGAs. CPLDs use a classic PLA-style AND/OR macro cell fabric with non-volatile on-chip storage, giving them instant-on configuration, deterministic timing, and immunity to configuration memory corruption. The MAX 9000 family is the high-density, high-I/O extension of the classic Altera MAX architecture, providing predictable timing suitable for glue logic, bus interfacing, and state-machine decoding in industrial and telecommunications systems. Key features of the EPM9480RC208-20 include a 20 ns worst-case pin-to-pin delay through the Logic Array Blocks (LABs), 560 macro cells distributed across 16 LABs, and a maximum operating frequency of approximately 117.6 MHz for registered logic. The device operates from a 5V core supply with 5V-tolerant I/O on most pins, supports in-system programmability via the IEEE 1149.1 JTAG interface, and integrates a JTAG-based boundary-scan test capability for board-level test access. Architecturally, the EPM9480RC208-20 uses Altera's classic MAX 9000 multi-LAB structure with a global Programmable Interconnect Array (PIA) that routes signals between LABs with predictable delay. Each macro cell contains a programmable AND/OR array, a flip-flop, and a configurable I/O architecture, allowing designers to implement both combinatorial and registered logic with consistent timing regardless of placement. Typical applications include bus-interface and protocol-bridge logic (PCI, ISA, VME), address decoding and wait-state generation for microprocessors, glue logic between processors and peripherals, industrial control state machines, and legacy telecommunications backplane design. The instant-on non-volatile configuration makes the MAX 9000 family especially suited for applications where FPGA configuration time is unacceptable. When designing with the EPM9480RC208-20, ensure the 5V supply rail is well-decoupled with 0.1 uF ceramic capacitors placed close to each VCC pin group, and observe the 208-pin RQFP thermal envelope when operating at high toggle rates. Use the Altera MAX+PLUS II or Quartus design toolchain for entry, fitting, and JTAG programming. Designers migrating to newer products should evaluate MAX II or MAX V CPLDs as modern, lower-power alternatives. This page synthesizes distributor pricing from Octopart and DigiKey listings, drop-in pin-compatible alternatives from the same Altera MAX 9000 family, and practical design considerations not duplicated from the manufacturer datasheet.
EPM9480RC240-15 - MAX 9000 CPLD 480 Macro Cells 15ns | Altera
The Altera EPM9480RC240-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 480 macro cells, 12,000 usable gates, and a 15 ns pin-to-pin propagation delay, housed in a 240-pin RQFP (32x32 mm) package operating from a 5.0 V supply. It is an in-system programmable (ISP) EEPROM-based PLD built on third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL. CPLDs sit between simple PLDs and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> programmable logic device -> digital IC. MAX 9000 devices use EEPROM configuration cells, so they retain their design without an external boot PROM and are live within microseconds of power-up. Key features include 480 macro cells, 12,000 usable gates, 15 ns pin-to-pin delay (tPD), 5.0 V in-system programmability through a built-in IEEE Std. 1149.1 JTAG interface, and 4.75 V to 5.25 V internal supply operation. The 240-pin RQFP package provides up to 191 user I/O pins, enabling wide bus interfaces in a single device. The MAX 9000 architecture uses a Multiple Array MatriX of logic array blocks (LABs) interconnected by a fast, predictable routing structure. Because timing is fixed and deterministic, EPM9480RC240-15 designs do not require the timing closure iterations typical of SRAM-based FPGAs, which simplifies worst-case timing analysis for 5 V legacy systems. Typical applications include 5 V industrial control glue logic, ISA/PCI bus bridging, legacy telecom line-card control, test and measurement instrumentation, and replacement of discrete 74-series logic in existing designs. The 15 ns speed grade suits moderate-speed state machines and address decoding. When designing with this device, note that the MAX 9000 family is a mature, non-RoHS 5 V technology; verify availability and plan for a lifecycle strategy. Decouple every VCC pin with a 0.1 uF ceramic capacitor placed close to the package. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for the EPM9480RC240-15.
EPM9480RC240-20 - 480-Macrocell MAX 9000 CPLD, 240-RQFP | Altera
The Altera EPM9480RC240-20 is a 480-macrocell, 10,000-usable-gate Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 240-pin RQFP (Power Quad Flat Pack) package. Built on a third-generation Multiple Array MatriX (MAX) architecture in high-performance CMOS EEPROM technology, the device delivers a 20 ns maximum pin-to-pin propagation delay (tpd) and supports in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. The part operates from a 4.75 V to 5.25 V internal supply and supports configurable I/O signaling at 3.3 V or 5 V to bridge mixed-voltage system designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-backed programmable logic device that sits in the hierarchy between simple PLDs (PAL/GAL) and high-density FPGAs. Compared with FPGAs, CPLDs offer deterministic timing, instant-on non-volatile configuration, and superior I/O count per dollar for glue-logic, bus-interface, and state-machine tasks. The MAX 9000 family is Altera's high-density CPLD line, integrating multiple Logic Array Blocks (LABs) connected via a programmable interconnect array (PIA) and is used in system-level logic integration where multiple PAL/GAL or 22V10 devices would otherwise be needed. Key features include 480 macrocells (with 676 flip-flops per MAX 9000 family), 10,000 usable gates, 175 user I/O pins, a 100 MHz maximum clock frequency on related -C variants, and CMOS EEPROM technology. The 240-pin RQFP (32x32 mm) package provides mechanical robustness and a generous PCB footprint suitable for prototype boards and industrial backplane designs. The architecture integrates PAL/GAL/22V10-equivalent blocks plus FPGA-class functionality into a single non-volatile device. Typical applications include industrial bus interface bridging, legacy glue-logic consolidation (replacing multiple PAL/GAL/22V10 devices), state-machine controllers, address decoding, power-up sequencing for multi-rail systems, and telecom backplane controllers. Designers often select the MAX 9000 family when non-volatile instant-on behavior and deterministic 20 ns timing are required, and when 175+ I/O pins are needed in a single device. When designing with this part, perform a complete thermal analysis because the 240-pin RQFP package dissipates more power than smaller BGA packages. Reference Altera Application Note 74 (Evaluating Power for Altera Devices) for power budgeting. Use the JTAG interface (IEEE 1149.1) for in-system programming and boundary-scan test; ensure your programmer supports MAX 9000 ISP via the ByteBlaster or compatible cable. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 9000 family, and practical design notes not found in the manufacturer datasheet itself.
EPM9560ABC356-10 - MAX 9000 CPLD, 560 Macrocells, 356-BGA | Altera
The Altera (Intel) EPM9560ABC356-10 is a high-density CMOS EEPROM-based CPLD from the MAX 9000 device family, delivering 12,000 usable gates and 560 macrocells in a 356-ball LBGA package with 216 user I/Os. The "-10" speed grade corresponds to a 10 ns pin-to-pin logic delay and supports internal counter frequencies up to 144 MHz, making it one of the highest-density members of the legacy MAX 9000A family. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/GAL-like macrocell arrays on a single die with a global interconnect fabric. Architecturally, a CPLD sits between simple SPLDs/GALs and high-density FPGAs in the programmable logic taxonomy: SPLD < CPLD < FPGA. The MAX 9000A family uses Altera's third-generation Multiple Array MatriX (MAX) architecture with dual-output macrocells that allow independent use of combinatorial and registered logic on each output. Key features of the EPM9560ABC356-10 include 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface, 35 Logic Array Blocks (LABs), full PCI Local Bus Specification Revision 2.2 compliance for plug-and-play peripheral designs, and operation from a single 4.75 V to 5.25 V supply. Commercial temperature grade (0 °C to 70 °C) and a 356-LBGA (35 x 35 mm) surface-mount package suit it for high-I/O glue-logic and bus-interface designs. From a technical perspective, each macrocell contains a programmable AND/OR array, a flip-flop, and dual outputs that can drive registered and combinatorial paths independently. The 10 ns tPD and 144 MHz fCNT enable the device to meet PCI 2.2 timing constraints at 33 MHz without wait-state insertion. 5-V ISP allows board-level reconfiguration through the JTAG chain, eliminating the need for an external PROM programmer and supporting manufacturing flow updates. Typical applications include PCI bus interface and bridge logic, high-performance glue logic between processors and peripherals, bus multiplexing and address decoding, and legacy industrial control systems. The high I/O count (216 user I/Os) and PCI compliance make it especially valuable where dense, deterministic logic is required between processors, memory, and peripheral ASICs. When designing with the EPM9560ABC356-10, ensure the JTAG chain integrity and provide clean 5 V power with adequate decoupling. Engineers migrating to newer designs should note that the MAX 9000 family is mature/legacy - verify long-term supply before new product introduction and consider MAX II or MAX V devices for new designs unless exact pin compatibility is required. This page synthesizes distributor inventory, parametric alternatives, and practical design notes not found in the original Altera datasheet alone.
EPM9560ARC208-10 - MAX 9000 CPLD 560 Macro 208-RQFP | Intel
The Intel (Altera) EPM9560ARC208-10 is a MAX 9000A family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and 153 user I/O pins in a 208-pin RQFP (PowerQuad/plastic quad flat pack) package, with a 10 ns pin-to-pin propagation delay and 5.0 V CMOS EEPROM-based in-system programmability. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks and a programmable interconnect matrix on a single die, providing deterministic non-volatile logic that is active immediately at power-up. In the logic hierarchy, a CPLD sits between simple glue logic (PAL/GAL) and full FPGAs: CPLDs offer lower density but predictable timing, single-chip non-volatility, and no external configuration memory. The MAX 9000 family uses a third-generation Multiple Array MatriX (MAX) architecture with EEPROM cells, so configuration is retained without a battery or boot PROM. Key features of the EPM9560ARC208-10 include 560 macrocells organized into 35 logic array blocks, 12,000 usable gates, 153 user I/O pins, a 10 ns maximum pin-to-pin propagation delay (speed grade -10), and an internal frequency of up to 144.9 MHz. The device operates from a 5.0 V supply and is specified over the commercial 0 C to +70 C temperature range. In-system programmability (ISP) via the IEEE 1149.1 JTAG boundary-scan interface allows field upgrades without removing the device from the board. The MAX 9000 architecture routes signals through a programmable interconnect array that provides uniform, predictable delays, unlike segmented FPGA routing. This makes the EPM9560ARC208-10 well suited to address decoding, bus bridging, state machines, and legacy glue-logic consolidation where deterministic timing matters more than raw gate count. The 208-pin RQFP package with exposed pad supports surface mounting and provides a manageable thermal path for the 5 V CMOS core. Typical applications include industrial control backplanes, telecommunications line cards, test-and-measurement instruments, and legacy system maintenance where an existing MAX 9000 design must be reproduced or repaired. Because the MAX 9000 family is mature, designers should confirm lifecycle status and consider pin-compatible MAX 9000A speed-grade variants or a migration path to MAX II/MAX V devices for new designs. When designing with this device, decouple every VCC pin with a 0.1 uF ceramic capacitor placed close to the pin, and provide a clean 5.0 V rail with less than 5% ripple. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560ARC208-10N - MAX 9000 CPLD 560 Macro 208-RQFP | Altera
The Altera EPM9560ARC208-10N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 12,000 usable gates, 153 user I/O pins, and a 10 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad II) package. It is a 5 V in-system-programmable EEPROM-based PLD built on Altera's third-generation MAX architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the architectural structure of a PAL with the density and flexibility of an FPGA. CPLDs sit between simple glue logic and full FPGAs in the programmable logic hierarchy: they offer non-volatile configuration, deterministic pin-to-pin timing, and low standby power, making them ideal for address decoding, bus bridging, state machines, and interface glue. The MAX 9000 family extends this concept to 6,000-12,000 usable gates with counter speeds up to 144 MHz. Key features of the EPM9560ARC208-10N include 560 macrocells organized in 20 LABs, 153 user I/O pins, 10 ns pin-to-pin delay, 144.9 MHz internal counter frequency, and 5 V CMOS EEPROM technology that retains configuration without an external boot device. The EEPROM-based architecture allows in-system programming (ISP) via the JTAG interface, eliminating the need for a separate configuration PROM. The MAX 9000 architecture uses a Multiple Array MatriX (MAX) structure with product-term logic, providing predictable timing independent of routing. This deterministic timing behavior is a key advantage over SRAM-based FPGAs for safety-critical and real-time control applications where worst-case delay must be guaranteed. Typical applications include industrial control backplanes, telecommunications line cards, PCI/ISA bus interfaces, instrumentation front-ends, and legacy system replacement where 5 V logic compatibility is required. The 208-pin RQFP package provides 153 I/O pins for wide bus interfacing. When designing with this device, note that it is a 5 V core part and requires 5 V supply rails; level shifting is needed when interfacing with 3.3 V or lower logic. The EEPROM configuration is retained for over 20 years, but the device is now obsolete and should be designed out for new projects. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for replacement and migration decisions.