EPM9320LI84-20 - MAX 9000 CPLD, 320 Macro, 60 I/O | Altera
N.º da peça: EPM9320LI84-20 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $28.5 | $28,50 |
| 10 | $24.75 | $247,50 |
| 100 | $19.9 | $1.990,00 |
| 500 | $15.4 | $7.700,00 |
| 1.000 | $12.8 | $12.800,00 |
EPM9320LI84-20 Visão geral
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks on a single chip with a programmable interconnect matrix. Within the broader taxonomy, a CPLD sits between small PLDs (PALs, GALs) and FPGAs: it provides fast, deterministic propagation delay (typically 5-20 ns regardless of routing), non-volatile on-chip configuration, and high-drive I/O suitable for bus interfacing and glue-logic replacement. CPLDs are commonly used as address decoders, bus interface bridges, state machines, and configuration controllers in microprocessor and DSP systems. The MAX 9000 family specifically targets high-density glue-logic consolidation, replacing multiple discrete PALs with a single device.
Key differentiating features of the EPM9320LI84-20 include its 320-macrocell capacity (the highest density in the MAX 9000 family), 60 user I/Os with 5-V tolerant I/O banks, and an internal operating frequency of up to 118 MHz. The 20 ns tPD is suitable for memory interface glue logic, peripheral controllers, and bus arbitration functions running at up to 50 MHz. The device supports the familiar Altera MAX+PLUS II and Quartus development flows and is pin-compatible with the MAX 9000 LC and GC speed/package variants in the same 84-PLCC pinout, simplifying second-source qualification and lifecycle migration planning.
Typical applications include high-density address decoding for 32-bit and 64-bit microprocessor systems, peripheral bus interfacing (PCI, ISA, VME bridges), state-machine controllers for industrial automation, JTAG-based ISP configuration of downstream devices, and legacy logic consolidation where a board was originally implemented with multiple 22V10 or 32-macrocell PALs. The non-volatile EEPROM configuration means the device powers up in a known state without an external boot PROM, simplifying system bring-up.
When designing with this part, note that the -20 speed grade is the slowest in the MAX 9000 family; for higher throughput, designers should consider the -15 or -10 variants. The 84-PLCC package requires a socket or careful reflow profiling because of the J-lead thermal mass, and JTAG chain ordering should be planned before PCB layout to avoid contention with other boundary-scan devices.
This page synthesizes distributor pricing as of 2026-09-13, pin-compatible MAX 9000 family alternatives from the same 84-PLCC footprint, and practical design notes drawn from the Altera MAX 9000 datasheet family - information not assembled in any single manufacturer document.
Alternativas drop-in para EPM9320LI84-20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM9320LI84-20 (mesmo formato e footprint) — diferindo em Mounting Type, Package, Supply Voltage (VCC), Architecture, Process Technology.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM9320LC84-15
✅ Drop-In✓ Em estoque
$17.95 / unidade
Ver ficha técnica →EPM9320LC84-10
✅ Drop-In✓ Em estoque
$84.96 / unidade
Ver ficha técnica →EPM9320LC84-20
✅ Drop-In✓ Em estoque
$9.75 / unidade
Ver ficha técnica →EPM9320LC84-20N
✅ Drop-In✓ Em estoque
$10.25 / unidade
Ver ficha técnica →EPM9320ALC84-10
✅ Drop-In✓ Em estoque
$19.8 / unidade
Ver ficha técnica →EPM9320ALI84-10
✅ Drop-In✓ Em estoque
$19.95 / unidade
Ver ficha técnica →EPM9320LI84-20 Classificações máximas e características elétricas
| Manufacturer | Altera (acquired by Intel) |
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| User I/Os | 60 |
| Encapsulamento | 84-PLCC (J-Lead, plastic LCC) |
| Propagation Delay (tPD) | 20 ns |
| Internal Frequency | 118 MHz |
| Tensão de alimentação | 5.0 V |
| Logic Family | CMOS, EEPROM-based |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Temperatura de operação | -40 C to +85 C (industrial) |
| Tipo de montagem | Surface Mount (PLCC socket-compatible) |
| Process Technology | High-performance CMOS EEPROM |
Configuração de pinos do EPM9320LI84-20
| Pino 1 | I/O — User I/O - bank A |
| Pino 2 | I/O — User I/O - bank A |
| Pino 3 | I/O — User I/O - bank A |
| Pino 4 | I/O — User I/O - bank A |
| Pino 5 | I/O — User I/O - bank A |
| Pino 6 | I/O — User I/O - bank A |
| Pino 7 | I/O — User I/O - bank A |
| Pino 8 | I/O — User I/O - bank A |
| Pino 9 | I/O — User I/O - bank A |
| Pino 10 | I/O — User I/O - bank A |
| Pino 11 | GND — Ground |
| Pino 12 | I/O — User I/O - bank B |
| Pino 13 | I/O — User I/O - bank B |
| Pino 14 | I/O — User I/O - bank B |
| Pino 15 | I/O — User I/O - bank B |
| Pino 16 | I/O — User I/O - bank B |
| Pino 17 | I/O — User I/O - bank B |
| Pino 18 | I/O — User I/O - bank B |
| Pino 19 | I/O — User I/O - bank B |
| Pino 20 | I/O — User I/O - bank B |
| Pino 21 | I/O — User I/O - bank B |
| Pino 22 | I/O — User I/O - bank B |
| Pino 23 | I/O — User I/O - bank B |
| Pino 24 | I/O — User I/O - bank B |
| Pino 25 | VCC — 5.0 V supply |
| Pino 26 | I/O — User I/O - bank C |
| Pino 27 | I/O — User I/O - bank C |
| Pino 28 | I/O — User I/O - bank C |
| Pino 29 | I/O — User I/O - bank C |
| Pino 30 | I/O — User I/O - bank C |
| Pino 31 | I/O — User I/O - bank C |
| Pino 32 | I/O — User I/O - bank C |
| Pino 33 | I/O — User I/O - bank C |
| Pino 34 | I/O — User I/O - bank C |
| Pino 35 | I/O — User I/O - bank C |
| Pino 36 | I/O — User I/O - bank C |
| Pino 37 | I/O — User I/O - bank C |
| Pino 38 | I/O — User I/O - bank C |
| Pino 39 | GND — Ground |
| Pino 40 | I/O — User I/O - bank D |
| Pino 41 | I/O — User I/O - bank D |
| Pino 42 | I/O — User I/O - bank D |
| Pino 43 | I/O — User I/O - bank D |
| Pino 44 | I/O — User I/O - bank D |
| Pino 45 | TDI — JTAG Test Data In |
| Pino 46 | I/O — User I/O - bank D |
| Pino 47 | I/O — User I/O - bank D |
| Pino 48 | I/O — User I/O - bank D |
| Pino 49 | I/O — User I/O - bank D |
| Pino 50 | I/O — User I/O - bank D |
| Pino 51 | I/O — User I/O - bank D |
| Pino 52 | I/O — User I/O - bank D |
| Pino 53 | I/O — User I/O - bank D |
| Pino 54 | GND — Ground |
| Pino 55 | I/O — User I/O - bank D |
| Pino 56 | I/O — User I/O - bank D |
| Pino 57 | TMS — JTAG Test Mode Select |
| Pino 58 | I/O — User I/O - bank D |
| Pino 59 | TCK — JTAG Test Clock |
| Pino 60 | I/O — User I/O - bank D |
| Pino 61 | I/O — User I/O - bank D |
| Pino 62 | VCC — 5.0 V supply |
| Pino 63 | I/O — User I/O - bank A |
| Pino 64 | I/O — User I/O - bank A |
| Pino 65 | I/O — User I/O - bank A |
| Pino 66 | I/O — User I/O - bank A |
| Pino 67 | I/O — User I/O - bank A |
| Pino 68 | I/O — User I/O - bank A |
| Pino 69 | I/O — User I/O - bank A |
| Pino 70 | I/O — User I/O - bank A |
| Pino 71 | I/O — User I/O - bank A |
| Pino 72 | I/O — User I/O - bank A |
| Pino 73 | I/O — User I/O - bank A |
| Pino 74 | GND — Ground |
| Pino 75 | I/O — User I/O - bank B |
| Pino 76 | I/O — User I/O - bank B |
| Pino 77 | I/O — User I/O - bank B |
| Pino 78 | I/O — User I/O - bank B |
| Pino 79 | I/O — User I/O - bank B |
| Pino 80 | I/O — User I/O - bank B |
| Pino 81 | I/O — User I/O - bank B |
| Pino 82 | I/O — User I/O - bank B |
| Pino 83 | TDO — JTAG Test Data Out |
| Pino 84 | I/O — User I/O - bank B |
Aplicações típicas
EPM9320LI84-20 é adequado para 6 aplicaçãos: High-Density Address Decoding for 32/64-bit Microprocessor Systems, Peripheral Bus Interface Bridge (PCI/ISA/VME), Industrial Automation State-Machine Controller, JTAG-Based In-System Configuration Controller for Downstream Devices, Legacy Multi-PAL Glue-Logic Consolidation, Telecommunications Backplane Glue Logic.
High-Density Address Decoding for 32/64-bit Microprocessor Systems
The EPM9320LI84-20's 320-macrocell capacity and 60 user I/Os make it well-suited to consolidate address decoding, chip-select generation, and wait-state insertion for 32-bit and 64-bit microprocessor/memory systems. A single device can replace ten or more discrete 22V10/32-macrocell PALs, shrinking board area and reducing BOM count. With 20 ns tPD, the part reliably decodes 50 MHz memory buses; engineers targeting higher speeds should select the -15 or -10 speed grade. The 84-PLCC package's high I/O count accommodates wide address buses (A0-A31) plus dedicated chip-select outputs without external steering logic. JTAG ISP enables post-layout logic changes without removing the part.
Recomendado
Peripheral Bus Interface Bridge (PCI/ISA/VME)
In legacy peripheral bus systems the EPM9320LI84-20 acts as a glue-logic bridge, generating control signals, managing bus arbitration, and providing timing-edge alignment between asynchronous peripherals. The 60 user I/Os comfortably accommodate full 32-bit data plus 32-bit address plus control (REQ#, GNT#, FRAME#, IRDY#) signals. The 5.0 V tolerant I/O matches PCI/ISA/VME logic levels directly without external transceivers. Non-volatile EEPROM configuration means the bridge comes up in a defined state without external boot PROMs. Industrial temperature rating supports telecom and industrial backplane applications. Pair with a supervisory reset device and bus transceivers for a complete bridge solution.
Recomendado
Industrial Automation State-Machine Controller
The EPM9320LI84-20 is well-suited to industrial state-machine controllers, where deterministic timing (CPLDs guarantee fixed 20 ns tPD regardless of logic utilization) is more important than raw gate count. Its 320 macrocells accommodate complex multi-state sequencers for PLC I/O modules, motor-control front-ends, and safety interlock logic. The industrial -40 C to +85 C temperature range supports factory-floor deployment. EEPROM non-volatility ensures the controller enters a known safe state at every power-up, critical for safety applications. The 84-PLCC package is socket-compatible for field replacement. JTAG ISP allows on-line firmware updates during commissioning without depaneling.
Recomendado
JTAG-Based In-System Configuration Controller for Downstream Devices
The EPM9320LI84-20 can serve as a master JTAG controller, sequencing configuration bitstreams to multiple downstream FPGAs, CPLDs, and boundary-scan devices. Its 320 macrocells implement the TAP controller state machine plus per-device instruction register management, while 60 I/Os drive TDI/TDO daisy-chains across multiple target devices. Non-volatile EEPROM configuration means the CPLD comes up as the JTAG master without an external processor. Industrial temperature grade supports outdoor and factory-floor installations. With 20 ns tPD, the part comfortably drives JTAG chains at the standard TCK rates. JTAG ISP for the CPLD itself uses the same chain.
Recomendado
Legacy Multi-PAL Glue-Logic Consolidation
Board designers often need to replace aging 22V10, 26V12, or 32-macrocell PALs whose silicon is end-of-life; the EPM9320LI84-20 provides 10x the logic density in a single 84-PLCC socket, directly replacing ten PALs. The non-volatile EEPROM means the consolidated design boots without an external PROM. JTAG ISP enables incremental port-by-port migration from discrete PALs: each migration step reprograms the CPLD with one additional PAL's logic, verified against the original part before removing it. Industrial temperature rating and PLCC packaging suit legacy systems whose sockets cannot accommodate leadless QFN/BGA packages.
Recomendado
Telecommunications Backplane Glue Logic
In telecom backplane applications the EPM9320LI84-20 provides high-density, deterministic glue logic for line-card interface controllers, where it manages HDB3/AMI encoding, clock-data recovery synchronization, and alarm-status multiplexing. The 5 V I/O directly interfaces with legacy telecom ASICs without level shifting, and the 60 user I/Os accommodate multi-port serial links plus parallel control/status buses. Industrial temperature rating and high reliability of EEPROM-based configuration suit carrier-grade equipment. The 84-PLCC package and through-hole-compatible socket mounting suit legacy backplane form factors that cannot accept fine-pitch SMT. JTAG ISP simplifies field firmware updates across geographically dispersed installations.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EPM9320LI84-20 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320LC84-20 | EPM9320LC84-20N | EPM9320ALC84-10 | EPM9320ALI84-10 |
|---|---|---|---|---|---|---|---|
| Package | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Propagation Delay (tPD) | 20 ns | 15 ns | 10 ns | 20 ns | 20 ns | 10 ns | 10 ns |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/Os | 60 | 60 | 60 | 60 | 60 | 60 | 60 |
| Operating Temperature | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (extended) | -40 C to +85 C (industrial) |
| Architecture | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Lifecycle Status | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB |
Principais diferenciais
- Industrial temperature grade in the -20 speed pinout (vs EPM9320LC84-20)
- Highest-density 84-PLCC MAX 9000 device with ISP (vs EPM7160SLC84-10)
- Direct cross-generation drop-in compatibility (vs EPM9320LC84-15)
Notas de projeto
The 84-PLCC J-lead package has a 1.27 mm pitch and is most commonly used in through-hole sockets; for surface-mount reflow, profile the package to JEDEC J-STD-020 MSL-3 conditions with a peak body temperature of 245 C and 60 s above 183 C. PLCC sockets from 3M, AMP, and Yamaichi accept this device and simplify field replacement; however, the socket adds ~6 pF per pin which may impact high-speed signal edges above 50 MHz. Reserve a JTAG header on every board that uses this device, even in production: the 5-pin header (TCK/TMS/TDI/TDO/GND) enables in-field firmware updates without depaneling.
Although the MAX 9000 architecture guarantees fixed 20 ns tPD regardless of routing, the I/O buffers do not have slew-rate control. For signals crossing PLCC socket inductance (estimated 6-10 nH per pin), add 33 ohm series damping resistors near the CPLD outputs when driving buses longer than 50 mm or above 25 MHz. Decouple each VCC pin (pins 25 and 62) with a 100 nF X7R ceramic plus a 10 uF tantalum bulk capacitor placed within 5 mm of the pin. Multiple GND pins (11, 39, 54, 74) should each have a dedicated via to the ground plane; do not share GND returns with high-current switching circuits.
Three pitfalls to avoid when designing with the EPM9320LI84-20. First, do not assume speed-grade compatibility across the family: substituting a -10 (10 ns) device into a board designed for the -20 (20 ns) without re-running timing simulation may produce hold-time violations in fast paths; always re-fit the design for the actual speed grade. Second, the MAX 9000 ISP programming algorithm requires VCC within 4.75-5.25 V during JTAG operations; out-of-spec voltage causes programming failures that may appear as silent bit-cell corruption. Third, when using the device as a JTAG master for downstream devices, ensure the CPLD is first in the JTAG chain (TDI input) so it can sequence the chain without contention; misordered chains cause BYPASS register corruption.
Informações de conformidade
RoHS/REACH status not stated in distributor pages. The EPM9320LI84-20N suffix variant denotes lead-free / Pb-free reflow-rated assembly; base EPM9320LI84-20 was originally released in SnPb finish. Contact Intel/Altera legacy support for formal RoHS/REACH documentation. AEC-Q100 not applicable - this is a commercial/industrial programmable logic device, not an automotive-grade IC.
