Intel

EPM9320RI208-20 - MAX 9000 CPLD, 320 Macrocells, 20ns | Intel

N.º da peça: EPM9320RI208-20 ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

5.0 V Vdss 208-pin RQFP (Power Quad Flat Pack) Package 100 MHz Speed

A partir de $18.95 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-13

Preços por volume

Qtd.	Preço unitário	Total
1	$38.5	$38,50
10	$32.75	$327,50
100	$27.2	$2.720,00
500	$22.4	$11.200,00
1.000	$18.95	$18.950,00

ℹ️ Todos os preços estão em USD

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EPM9320RI208-20 Visão geral

The Intel (formerly Altera) EPM9320RI208-20 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, housed in a 208-pin RQFP package with 320 macro cells, 6,000 usable gates, and a 20 ns pin-to-pin propagation delay. The device is built on Altera's third-generation Multiple Array MatriX (MAX) architecture and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface.

A CPLD (Complex Programmable Logic Device) is a non-volatile, instantaneously-on programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a programmable interconnect matrix. CPLDs sit hierarchically below FPGAs in the programmable logic taxonomy, offering deterministic timing, lower power, and simpler glue-logic integration than FPGAs, while delivering far higher logic density than legacy SPLDs/PALs. They are commonly used as bus bridges, address decoders, and state-machine controllers in digital systems.

Key features of the EPM9320RI208-20 include four dedicated low-skew global input pins (typically used for clocks, clear, and output-enable distribution), a maximum internal operating frequency of 100 MHz, in-system programmability via JTAG, and industrial-grade temperature operation. The 5.0-V VCCIO core supply makes it directly compatible with TTL/CMOS logic families popular in legacy industrial designs.

The MAX 9000 architecture employs an enhanced EEPROM process and a fast interconnect matrix to deliver predictable timing across all 320 macro cells. Each Logic Array Block (LAB) contains 16 macro cells feeding the Programmable Interconnect Array (PIA), and the device includes 52 I/O pins in the 208-pin RQFP footprint with multiple I/O standards supported.

Typical applications include industrial automation controllers, glue-logic integration in microprocessor designs, bus-interface bridging, address decoding, and state-machine implementation in telecommunications and embedded systems. The non-volatile EEPROM configuration cell ensures instant-on behavior with no external boot PROM required.

When designing with this device, ensure that VCC rises monotonically during power-up and that the JTAG pins (TDI, TMS, TCK, TDO) are correctly terminated to support in-system programming. The four dedicated input pins provide low-skew clock distribution across the entire device and should be preferred for global timing signals.

This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet, enabling faster sourcing decisions for legacy 5-V MAX 9000 designs.

Alternativas drop-in para EPM9320RI208-20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM9320RI208-20 (mesmo formato e footprint) — diferindo em Package, In-System Programmability, Operating Temperature, RoHS Status, Usable Gates.

EPM9320ARI208-10N

Altera

Package: 208-pin RQFP (S-PQFP-G208)

Operating Temperature: -40 C to +85 C (industrial)

RoHS Status: unknown