Altera

EPM9320RI208-20N - MAX 9000 CPLD 320 Macrocell 208-PQFP | Altera

N.º da peça: EPM9320RI208-20N ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

5.0 V Vdss 208-pin PQFP (Plastic Quad Flat Pack) Package EEPROM (non-volatile) Memory

Contato para preços

MOQ: 1 |

Preço atualizado: 2026-09-13

Preços por volume

Qtd.	Preço unitário	Total
1	$0	$0,00
10	$0	$0,00
100	$0	$0,00
500	$0	$0,00
1.000	$0	$0,00

ℹ️ Todos os preços estão em USD

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EPM9320RI208-20N Visão geral

The Altera EPM9320RI208-20N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 320 macrocells, 484 flip-flops, and a 20 ns pin-to-pin propagation delay, housed in a 208-pin Plastic Quad Flat Pack (PQFP) package with 0.5 mm lead pitch. It is a 5.0 V EEPROM-based programmable logic device offering in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface.

A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks with a programmable interconnect matrix, allowing designers to implement custom digital logic functions without fabricating an ASIC. Within the programmable logic hierarchy, the CPLD sits between simple PLDs (PAL/GAL) and full FPGAs, offering non-volatile configuration, deterministic timing, and instant-on operation. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which uses EEPROM cells to retain configuration without an external boot device.

Key features of the EPM9320RI208-20N include 320 macrocells organized into Logic Array Blocks (LABs), 484 flip-flops, 5.0 V in-system programmability via JTAG, and four dedicated low-skew global input pins typically used for clock, clear, and output-enable distribution. The device supports 3.3 V or 5 V configurable I/O operation, making it suitable for mixed-voltage legacy systems. The industrial temperature grade (I suffix) covers -40C to +85C operation.

The MAX 9000 architecture routes signals through a programmable interconnect array that provides predictable, fixed pin-to-pin delays of 20 ns, eliminating the timing uncertainty found in SRAM-based FPGAs. This deterministic timing is critical for glue-logic replacement, bus interface, and state-machine applications where worst-case delay must be guaranteed.

Typical applications include legacy system glue logic, ISA/PCI bus interfaces, industrial control state machines, instrumentation front-end logic, and replacement of discrete 74-series logic. The 208-pin PQFP package provides up to 160 user I/O pins for wide bus interfaces.

When designing with this device, note that VCC must rise monotonically during power-up, and inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. The EPM9320RI208-20N is a mature, widely second-sourced part; verify lifecycle status before committing to new designs.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for replacement and design-in decisions.

Alternativas drop-in para EPM9320RI208-20N — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM9320RI208-20N (mesmo formato e footprint) — diferindo em Package, In-System Programmability, Usable Gates, Device Type, Macro Cells.

EPM9320RC208-15

Altera

Package: 208-pin RQFP (Power QFP)

In-System Programmability: Yes (ISP via JTAG)

Usable Gates: 6,000