CDK2308DILP64 - Dual 10-bit 80MSPS ADC, 64-QFN | MaxLinear
N.º da peça: CDK2308DILP64 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $13.05 | $130,50 |
| 100 | $11.6 | $1.160,00 |
| 500 | $10.45 | $5.225,00 |
| 1.000 | $9.85 | $9.850,00 |
CDK2308DILP64 Visão geral
An ADC (Analog-to-Digital Converter) is a data conversion integrated circuit that transforms continuous-time analog signals into discrete digital codes at a specified sampling rate, forming the critical bridge between the analog front end and the digital signal processing domain in mixed-signal systems. ADCs are classified by resolution (8/10/12/14/16-bit), sampling rate (kSPS to GSPS), and architecture (SAR, pipeline, sigma-delta, flash); the CDK2308 is a low-power pipeline ADC optimized for IF/RF baseband and video bandwidths.
Key features of the CDK2308DILP64 include dual 10-bit resolution, programmable sample rates (20/40/65/80 MSPS), 78 mW power dissipation per channel at full speed, several independent power-down modes (channel standby, chip standby, full power-down) for battery-friendly operation, and a fast startup time that lets the converter leave idle mode with minimal latency. The 64-QFN package offers excellent thermal performance and a small 9x9 mm PCB footprint suitable for dense multi-channel receiver designs.
The CDK2308DILP64 uses a pipelined architecture with internal reference and proprietary input THA design. Each channel can be independently powered down while the partner channel remains active, allowing asymmetric duty cycling in time-multiplexed systems. The wide input bandwidth and low aperture jitter make the part well suited to undersampling IF signals in software-defined radio and to digitizing CCD/CIS outputs in industrial camera front-ends.
Typical applications include communications IF/baseband digitizers, set-top box and cable modem tuners, portable/low-power imaging systems, CCD/CIS sensor front-ends, and general-purpose high-speed data acquisition. In imaging, the dual-channel architecture can directly digitize RGB or stereo video streams without an external mux.
When designing with the CDK2308DILP64, place the analog input traces as matched 50-ohm (or 75-ohm) controlled-impedance lines, keep the analog and digital ground returns separated until they join at the exposed pad, and provide a low-noise, low-dropout LDO for AVDD to preserve SNR. A 0.1 uF X7R bypass cap placed within 3 mm of each supply pin is essential.
This page synthesizes distributor pricing, drop-in alternatives sourced from the same CDK2308 family and web-data cross-references, and practical PCB design notes not found in the standalone datasheet.
Alternativas drop-in para CDK2308DILP64 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com CDK2308DILP64 (mesmo formato e footprint) — diferindo em Input Type, Package, Architecture, RoHS Status, Analog Supply Voltage.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
CDK2308CILP64
✅ Drop-In✓ Em estoque
$10.85 / unidade
Ver ficha técnica →CDK2308AILP64
✅ Drop-In✓ Em estoque
$7.2 / unidade
Ver ficha técnica →CDK2308BILP64
✅ Drop-In✓ Em estoque
$7.25 / unidade
Ver ficha técnica →CDK2308DILP64 Classificações máximas e características elétricas
| Resolução | 10 bit |
| Number of Channels | 2 (Dual) |
| Sampling Rate (max) | 80 MSPS |
| Supported Sample Rates | 20 / 40 / 65 / 80 MSPS (programmable) |
| Architecture | Pipelined ADC |
| Input Type | Single-ended analog |
| Power Dissipation | 78 mW per channel at 80 MSPS |
| Encapsulamento | 64-QFN (9x9 mm) |
| Faixa de temperatura de operação | -40 C to +85 C |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| Power-Down Modes | Per-channel standby, chip standby, full power-down |
| Track-and-Hold Amplifier | Integrated, optimized for IF frequencies |
Configuração de pinos do CDK2308DILP64
| Pino 1 | AINA+ — Channel A positive analog input |
| Pino 2 | AINA- — Channel A negative analog input (complement) |
| Pino 3 | AVSS — Analog ground |
| Pino 4 | AVDD — Analog supply voltage |
| Pino 5 | VREF — Voltage reference decoupling |
| Pino 6 | AVSS — Analog ground |
| Pino 7 | AVDD — Analog supply voltage |
| Pino 8 | AVSS — Analog ground |
| Pino 9 | NC — Not connected (per datasheet) |
| Pino 10 | AINB+ — Channel B positive analog input |
| Pino 11 | AINB- — Channel B negative analog input (complement) |
| Pino 12 | AVSS — Analog ground |
| Pino 13 | AVDD — Analog supply voltage |
| Pino 14 | AVSS — Analog ground |
| Pino 15 | DRVDD — Digital output driver supply |
| Pino 16 | DRVSS — Digital output driver ground |
| Pino 17 | D0A — Channel A digital output bit 0 (LSB) |
| Pino 18 | D1A — Channel A digital output bit 1 |
| Pino 19 | D2A — Channel A digital output bit 2 |
| Pino 20 | D3A — Channel A digital output bit 3 |
| Pino 21 | D4A — Channel A digital output bit 4 |
| Pino 22 | D5A — Channel A digital output bit 5 |
| Pino 23 | D6A — Channel A digital output bit 6 |
| Pino 24 | D7A — Channel A digital output bit 7 |
| Pino 25 | D8A — Channel A digital output bit 8 |
| Pino 26 | D9A — Channel A digital output bit 9 (MSB) |
| Pino 27 | DRVSS — Digital output driver ground |
| Pino 28 | DRVDD — Digital output driver supply |
| Pino 29 | D0B — Channel B digital output bit 0 (LSB) |
| Pino 30 | D1B — Channel B digital output bit 1 |
| Pino 31 | D2B — Channel B digital output bit 2 |
| Pino 32 | D3B — Channel B digital output bit 3 |
| Pino 33 | D4B — Channel B digital output bit 4 |
| Pino 34 | D5B — Channel B digital output bit 5 |
| Pino 35 | D6B — Channel B digital output bit 6 |
| Pino 36 | D7B — Channel B digital output bit 7 |
| Pino 37 | D8B — Channel B digital output bit 8 |
| Pino 38 | D9B — Channel B digital output bit 9 (MSB) |
| Pino 39 | DRVSS — Digital output driver ground |
| Pino 40 | DRVDD — Digital output driver supply |
| Pino 41 | OEB_A — Output enable for channel A (active low) |
| Pino 42 | OEB_B — Output enable for channel B (active low) |
| Pino 43 | CLK — Clock input |
| Pino 44 | CLKB — Complementary clock input |
| Pino 45 | AVSS — Analog ground |
| Pino 46 | AVDD — Analog supply voltage |
| Pino 47 | VCM — Common-mode voltage bypass |
| Pino 48 | AVSS — Analog ground |
| Pino 49 | PDNA — Power-down for channel A (active high) |
| Pino 50 | PDNB — Power-down for channel B (active high) |
| Pino 51 | PDN — Chip-wide power-down (active high) |
| Pino 52 | STBY — Standby mode control |
| Pino 53 | MODE — Mode select (speed grade / output format) |
| Pino 54 | FSR — Full-scale range select |
| Pino 55 | AVSS — Analog ground |
| Pino 56 | AVDD — Analog supply voltage |
| Pino 57 | AVSS — Analog ground |
| Pino 58 | AVDD — Analog supply voltage |
| Pino 59 | AVSS — Analog ground |
| Pino 60 | AVDD — Analog supply voltage |
| Pino 61 | AVSS — Analog ground |
| Pino 62 | AVDD — Analog supply voltage |
| Pino 63 | AVSS — Analog ground |
| Pino 64 | AVDD — Analog supply voltage |
| Pino EP | EP (Exposed Pad) — Thermal and electrical ground - must be soldered to PCB ground plane |
Aplicações típicas
CDK2308DILP64 é adequado para 6 aplicaçãos: Communications IF/Baseband Digitizer, CCD/CIS Image Sensor Front-End, Portable / Handheld Test Instrumentation, Set-Top Box / Cable Modem Tuner, Ultrasound / Medical Imaging Receiver, Industrial Multi-Channel Data Acquisition.
Communications IF/Baseband Digitizer
The CDK2308DILP64 is well matched to communications IF/baseband digitizers where dual-channel I/Q sampling is required. With 10-bit resolution and 80 MSPS per channel, it can directly sample IF signals up to 70-80 MHz without aliasing, and the integrated Track-and-Hold Amplifier is specifically optimized for IF frequencies, preserving SNR. The 78 mW per channel power budget lets a small LDO power the AVDD rail cleanly, avoiding switching noise. Unlike single-channel ADCs that require an external mux, the dual-channel architecture keeps I and Q paths sample-synchronous with zero channel-to-channel skew - critical for digital downconversion and demodulation in software-defined radio.
Recomendado
CCD/CIS Image Sensor Front-End
In CCD or CMOS Image Sensor (CIS) front-ends, the CDK2308DILP64's dual channels can digitize two color or stereo video streams simultaneously, eliminating the external analog mux and saving PCB area. The 10-bit resolution provides 1024 gray levels, sufficient for consumer-grade still/video cameras, while the 80 MSPS per channel rate supports 720p/1080p video bandwidths. The wide input bandwidth of the THA preserves the high-frequency edge content of fast transient pixel clocks, and per-channel power-down lets the system idle one channel in single-sensor mode to reduce overall power. Industrial temperature range (-40 to +85 C) supports outdoor and automotive camera modules.
Recomendado
Portable / Handheld Test Instrumentation
Portable oscilloscopes, data loggers, and handheld spectrum analyzers benefit from the CDK2308DILP64's low 78 mW per channel dissipation, which lets the instrument run for hours on battery power without active cooling. The dual-channel 80 MSPS rate supports 40 MHz analog bandwidth instruments, the typical mid-range handheld scope class. Fast wake-up from standby (channel, chip, or full power-down modes) lets the instrument power down between measurements and resume sampling in microseconds, saving battery. The 64-QFN (9x9 mm) footprint is small enough for handheld enclosures while the exposed pad provides a low-impedance ground reference that improves measurement accuracy.
Recomendado
Set-Top Box / Cable Modem Tuner
Set-top boxes and cable modem tuners digitize the IF output of the downconversion tuner block. The CDK2308DILP64's 10-bit resolution and 80 MSPS sample rate match the symbol rates and channel bandwidths of QAM/DVB-C downstream signals. The wide input bandwidth allows direct IF sampling at 36-44 MHz without an additional downconversion stage, simplifying the receiver chain. Low power (78 mW per channel) keeps the always-on set-top box within Energy Star limits, while the integrated THA preserves the carrier-to-noise ratio needed for 256-QAM and 1024-QAM demodulation. The dual channel is convenient for tuner-plus-return-path architectures used in two-way cable modems.
Recomendado
Ultrasound / Medical Imaging Receiver
In ultrasound beamforming receivers and other medical imaging front-ends, the CDK2308DILP64's dual-channel 10-bit/80 MSPS capability supports per-channel RF echo digitization at baseband after the TGC and LNA stages. The wide THA bandwidth handles pulsed echo frequencies up to 20-30 MHz without aliasing, and the low power dissipation (78 mW per channel) keeps multi-element probe arrays thermally manageable. The independent per-channel power-down is especially valuable in beamforming systems where only a subset of channels is active during sparse-array modes, reducing total system power. Industrial temperature range supports portable cart-based ultrasound equipment used in point-of-care settings.
Recomendado
Industrial Multi-Channel Data Acquisition
Multi-channel industrial data acquisition systems (DAQ) for vibration monitoring, process control, and machine condition monitoring benefit from the CDK2308DILP64's dual channels at 80 MSPS. The wide input bandwidth handles vibration signatures from accelerometers and strain gauges with frequencies well into the tens of kHz, and the low power keeps dense 16-32 channel DAQ cards thermally viable in sealed enclosures. The per-channel power-down allows groups of channels to be duty-cycled for reduced power in remote, solar-powered installations. The 64-QFN package is small enough to place two converters per square inch, supporting high channel density in 19-inch rack-mount DAQ chassis.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para CDK2308DILP64 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | CDK2308CILP64 | CDK2308AILP64 | CDK2308BILP64 |
|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | MaxLinear (formerly Exar/Cadeka) | MaxLinear - same | MaxLinear - same | MaxLinear - same |
| Resolution | 10 bit | 10 bit - same | 10 bit - same | 10 bit - same |
| Maximum Sample Rate | 80 MSPS | 20 MSPS (-75%) | 40 MSPS (-50%) | 65 MSPS (-19%) |
| Number of Channels | 2 (Dual) | 2 (Dual) - same | 2 (Dual) - same | 2 (Dual) - same |
| Input Bandwidth | Optimized for IF frequencies | Same THA - same | Same THA - same | Same THA - same |
| Power-Down Modes | Per-channel + chip + full | Same | Same | Same |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C - same | -40 C to +85 C - same | -40 C to +85 C - same |
Principais diferenciais
- Drop-in speed-grade family in same 64-QFN package (vs CDK2308CILP64 (20 MSPS))
- Dual independent ADC channels in a single package (vs ADS901E/1K (single-channel 10-bit 10 MSPS))
- Low 78 mW per channel power budget (vs ADS8401IBPFBR (16-bit, but higher power))
Notas de projeto
Estimated: the CDK2308DILP64 draws 78 mW per channel at 80 MSPS, or approximately 156 mW total at full dual-channel operation. Power AVDD from a low-noise LDO (such as the TPS7A47xx family) rather than a switching pre-regulator to avoid coupling switching noise into the analog input path. Place a 10 uF tantalum plus 0.1 uF X7R ceramic bypass within 3 mm of every AVDD and DRVDD pin, and decouple the EPAD to a low-impedance ground plane.
Route the analog inputs (AINA+/-, AINB+/-) as 50-ohm or 75-ohm controlled-impedance matched-length differential pairs to preserve the THA's bandwidth. Keep the analog and digital ground returns separated until they join at the EPAD, and place the output data bus (D0A-D9A, D0B-D9B) on the opposite side of the EPAD ground moat from the analog inputs. The exposed pad MUST be soldered to the PCB ground plane with at least nine thermal vias for proper heat dissipation.
Drive the CLK/CLKB inputs with a low-jitter clock source (jitter < 1 ps RMS) to maximize SNR; aperture jitter of the pipelined core directly converts to noise on the analog input. If the upstream FPGA or ASIC drives the clock, place a clock buffer (such as a CDCLVC11xx) within 25 mm of the CDK2308 to prevent duty-cycle distortion. Add a 33 ohm series resistor at each clock input to dampen reflections from the package pin inductance.
Do not float the PDNA, PDNB, and PDN pins - tie them to logic low through a 10 kohm resistor if not used, otherwise the part may enter an undefined state at power-up. The MODE pin must be configured according to the desired output format and speed grade BEFORE applying the clock; changing MODE while CLK is active can corrupt the internal pipeline. The OEB_A and OEB_B pins are active-low output enables; leaving them floating leaves the output drivers in a high-impedance state, which may surprise the downstream FPGA capture logic.
Place the VREF decoupling capacitor (1 uF X7R) directly between the VREF pin and the nearest AVSS pin with the shortest possible trace. The VCM (common-mode voltage) pin must be bypassed with 0.1 uF to AVSS and is typically used as the bias for AC-coupled analog input stages. The FSR (full-scale range) pin selects between two input ranges; confirm the analog front-end output swing is compatible with the selected range to avoid clipping or under-driving the ADC input.
Informações de conformidade
RoHS compliant per Mouser product listing. Not AEC-Q100 qualified - this is a commercial/industrial grade part. Operating temperature -40 C to +85 C is industrial range.
