Intel
EPM9560WI208-20 - 560-Cell CPLD, 23.6ns, CQFP-208 | Intel / Altera
N.º da peça: EPM9560WI208-20 ✗ Fim de vida
Em estoque
Enviado em 1 a 3 dias úteis
CQFP-208 (Ceramic Quad Flat Pack) Package
-20 Speed
A partir de $105
USD / unidade
MOQ: 1 |
Preço atualizado: 2026-09-13
Preços por volume
| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $185 | $185,00 |
| 10 | $165 | $1.650,00 |
| 100 | $140 | $14.000,00 |
| 500 | $120 | $60.000,00 |
| 1.000 | $105 | $105.000,00 |
ℹ️ Todos os preços estão em USD
EPM9560WI208-20 Visão geral
The Intel / Altera EPM9560WI208-20 is a high-density 560-cell Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 208-pin Ceramic Quad Flat Pack (CQFP208) package with gull-wing leads. It provides 23.6ns pin-to-pin logic delay, 560 macrocells, 16 logic array blocks, and up to 212 user I/O pins for complex glue-logic, bus-interface, and state-machine designs. The device is built on a 0.35-micron CMOS EEPROM process and is rated for industrial temperature operation.
A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix. In the broader taxonomy it sits under programmable logic -> PLD -> CPLD -> MAX 9000 series -> high-density glue logic. CPLDs are commonly deployed as deterministic, low-latency controllers alongside microprocessors, FPGAs, and ASICs, providing boot configuration, address decoding, bus arbitration, and custom I/O expansion with predictable timing and instant-on behavior from on-chip EEPROM.
Key features of the EPM9560WI208-20 include 560 macrocells, 16 logic array blocks (LABs), 212 maximum user I/O pins, 23.6ns worst-case pin-to-pin propagation delay (tPD), a JTAG-based IEEE 1149.1 boundary-scan interface, and in-system programmability via JTAG. The internal EEPROM configuration cells allow instant-on operation at power-up without external boot memory, and the device is supported by the Altera MAX+PLUS II and Quartus design tools.
The MAX 9000 architecture splits the device into LABs connected by a programmable interconnect array (PIA). Each macrocell contains a programmable-AND/OR array, a flip-flop, and product-term steering, which gives the part deterministic 23.6ns timing across all paths. The 560-cell capacity places this device in the upper tier of the MAX 9000 family, suitable for designs that exceed the density of the MAX 7000 family but do not require an FPGA.
Typical applications include military and aerospace avionics, industrial process control, telecommunication line cards, and legacy bus-bridge designs. The ceramic CQFP-208 package is preferred in harsh-environment and high-reliability systems where plastic packages are not acceptable, including down-hole, military, and aerospace programs.
When designing with the EPM9560WI208-20, note that the -20 speed grade reflects 23.6ns tPD; faster -15 and -10 grades are available in the same MAX 9000 family for tighter timing budgets. Because this part is in the Ceramic QFP package with gull-wing leads, PCB layout must accommodate the larger pad geometry and inspect for lead coplanarity during assembly.
This page synthesizes distributor pricing, drop-in same-family alternatives, application guidance, and comparison data not aggregated in a single location on the Altera / Intel datasheet.
A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix. In the broader taxonomy it sits under programmable logic -> PLD -> CPLD -> MAX 9000 series -> high-density glue logic. CPLDs are commonly deployed as deterministic, low-latency controllers alongside microprocessors, FPGAs, and ASICs, providing boot configuration, address decoding, bus arbitration, and custom I/O expansion with predictable timing and instant-on behavior from on-chip EEPROM.
Key features of the EPM9560WI208-20 include 560 macrocells, 16 logic array blocks (LABs), 212 maximum user I/O pins, 23.6ns worst-case pin-to-pin propagation delay (tPD), a JTAG-based IEEE 1149.1 boundary-scan interface, and in-system programmability via JTAG. The internal EEPROM configuration cells allow instant-on operation at power-up without external boot memory, and the device is supported by the Altera MAX+PLUS II and Quartus design tools.
The MAX 9000 architecture splits the device into LABs connected by a programmable interconnect array (PIA). Each macrocell contains a programmable-AND/OR array, a flip-flop, and product-term steering, which gives the part deterministic 23.6ns timing across all paths. The 560-cell capacity places this device in the upper tier of the MAX 9000 family, suitable for designs that exceed the density of the MAX 7000 family but do not require an FPGA.
Typical applications include military and aerospace avionics, industrial process control, telecommunication line cards, and legacy bus-bridge designs. The ceramic CQFP-208 package is preferred in harsh-environment and high-reliability systems where plastic packages are not acceptable, including down-hole, military, and aerospace programs.
When designing with the EPM9560WI208-20, note that the -20 speed grade reflects 23.6ns tPD; faster -15 and -10 grades are available in the same MAX 9000 family for tighter timing budgets. Because this part is in the Ceramic QFP package with gull-wing leads, PCB layout must accommodate the larger pad geometry and inspect for lead coplanarity during assembly.
This page synthesizes distributor pricing, drop-in same-family alternatives, application guidance, and comparison data not aggregated in a single location on the Altera / Intel datasheet.
Alternativas drop-in para EPM9560WI208-20 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EPM9560WI208-20 (mesmo formato e footprint) — diferindo em Process Technology, Device Type, Package, Programming Interface, Operating Temperature Grade.
Altera
Process Technology: CMOS, electrically erasable
Device Type: EE Programmable Logic Device (CPLD)
Package: 208-pin CQFP (Ceramic Quad Flat Pack)
Comparar com EPM9560WI208-20 →
Altera
Device Type: EE PLD (Electrically Erasable Programmable Logic Device)
Package: 208-pin CQFP (Ceramic Quad Flat Pack)
Programming Interface: JTAG (IEEE 1149.1 boundary scan)
Comparar com EPM9560WI208-20 →
Altera
Process Technology: 0.35 µm CMOS EEPROM
Package: CQFP-208 (Ceramic Quad Flat Pack)
Programming Interface: IEEE 1149.1 JTAG
Comparar com EPM9560WI208-20 →
Altera
Process Technology: CMOS, EEPROM-based
Device Type: CPLD (EPLD)
Package: PQFP-208 (RQFP/WQFP)
Comparar com EPM9560WI208-20 →
Altera
Process Technology: CMOS, Electrically Erasable
Package: 208-pin CQFP (Ceramic Quad Flat Pack)
Programming Interface: JTAG BST (in-system programmable)
Comparar com EPM9560WI208-20 →
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EPM9560WC208-20
✅ Drop-InAltera
📦 CQFP-208
MAX 9000 · CPLD (EPLD) · 560 · 35 · 149 · 23.6 ns · PQFP-208 (RQFP/WQFP) · CMOS, EEPROM-based
✓ Em estoque
$25.8 / unidade
Ver ficha técnica →EPM9560WC208-20C
✅ Drop-InAltera
📦 CQFP-208
MAX 9000 (EE PLD) · EPM9560 · 560 · 35 · 149 · 20 ns · CMOS, Electrically Erasable
✓ Em estoque
$140 / unidade
Ver ficha técnica →EPM9560WC208-15
✅ Drop-InAltera
📦 CQFP-208
MAX 9000 · EE PLD (Electrically Erasable Programmable Logic Device) · CMOS · 560 · 35 · 772 · 149 · 117.6 MHz
✓ Em estoque
$105 / unidade
Ver ficha técnica →EPM9560WC208-15C
✅ Drop-InAltera
📦 CQFP-208
MAX 9000 · EPM9560 · 560 · 35 · 772 · 149 · 3.3 V or 5 V · 117.6 MHz
✓ Em estoque
$178 / unidade
Ver ficha técnica →EPM9560WC208
✅ Drop-InAltera
📦 CQFP-208
MAX 9000 · EE Programmable Logic Device (CPLD) · 560 · 35 · 772 · 149 · 117.6 MHz · 16.6 ns
✓ Em estoque
$125 / unidade
Ver ficha técnica →EPM9560WI208-20 Classificações máximas e características elétricas
| Device Family | MAX 9000 |
| Device Type | EE PLD / Complex Programmable Logic Device (CPLD) |
| Macrocells / Logic Cells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 |
| Pin-to-Pin Propagation Delay (tPD) | 23.6 ns |
| Speed Grade | -20 |
| Process Technology | 0.35 micron CMOS EEPROM |
| Programmability | In-system via JTAG (IEEE 1149.1) |
| Package Type | CQFP-208 (Ceramic Quad Flat Pack) |
| Terminal Form | Gull Wing |
| Number of Terminals | 208 |
| Package Code | QFP |
| Package Shape | Square |
| Operating Temperature Grade | Industrial |
| Tipo de montagem | Surface Mount |
| Design Tools | MAX+PLUS II, Quartus |
Configuração de pinos do EPM9560WI208-20
| Pino 1 | I/O — User I/O pin (function defined by user design) |
| Pino 2 | I/O — User I/O pin (function defined by user design) |
| Pino 3 | I/O — User I/O pin (function defined by user design) |
| Pino 4 | I/O — User I/O pin (function defined by user design) |
| Pino 5 | I/O — User I/O pin (function defined by user design) |
| Pino 6 | I/O — User I/O pin (function defined by user design) |
| Pino 7 | GND — Ground |
| Pino 8 | I/O — User I/O pin (function defined by user design) |
| Pino 9 | I/O — User I/O pin (function defined by user design) |
| Pino 10 | I/O — User I/O pin (function defined by user design) |
| Pino 11 | I/O — User I/O pin (function defined by user design) |
| Pino 12 | I/O — User I/O pin (function defined by user design) |
| Pino 13 | I/O — User I/O pin (function defined by user design) |
| Pino 14 | I/O — User I/O pin (function defined by user design) |
| Pino 15 | I/O — User I/O pin (function defined by user design) |
| Pino 16 | I/O — User I/O pin (function defined by user design) |
| Pino 17 | VCC — Supply voltage (5 V) |
| Pino 18 | I/O — User I/O pin (function defined by user design) |
| Pino 19 | I/O — User I/O pin (function defined by user design) |
| Pino 20 | I/O — User I/O pin (function defined by user design) |
| Pino 21 | I/O — User I/O pin (function defined by user design) |
| Pino 22 | I/O — User I/O pin (function defined by user design) |
| Pino 23 | I/O — User I/O pin (function defined by user design) |
| Pino 24 | I/O — User I/O pin (function defined by user design) |
| Pino 25 | I/O — User I/O pin (function defined by user design) |
| Pino 26 | I/O — User I/O pin (function defined by user design) |
| Pino 27 | I/O — User I/O pin (function defined by user design) |
| Pino 28 | I/O — User I/O pin (function defined by user design) |
| Pino 29 | GND — Ground |
| Pino 30 | I/O — User I/O pin (function defined by user design) |
| Pino 31 | I/O — User I/O pin (function defined by user design) |
| Pino 32 | I/O — User I/O pin (function defined by user design) |
| Pino 33 | I/O — User I/O pin (function defined by user design) |
| Pino 34 | I/O — User I/O pin (function defined by user design) |
| Pino 35 | I/O — User I/O pin (function defined by user design) |
| Pino 36 | I/O — User I/O pin (function defined by user design) |
| Pino 37 | I/O — User I/O pin (function defined by user design) |
| Pino 38 | I/O — User I/O pin (function defined by user design) |
| Pino 39 | I/O — User I/O pin (function defined by user design) |
| Pino 40 | I/O — User I/O pin (function defined by user design) |
| Pino 41 | I/O — User I/O pin (function defined by user design) |
| Pino 42 | I/O — User I/O pin (function defined by user design) |
| Pino 43 | VCC — Supply voltage (5 V) |
| Pino 44 | I/O — User I/O pin (function defined by user design) |
| Pino 45 | I/O — User I/O pin (function defined by user design) |
| Pino 46 | I/O — User I/O pin (function defined by user design) |
| Pino 47 | I/O — User I/O pin (function defined by user design) |
| Pino 48 | I/O — User I/O pin (function defined by user design) |
| Pino 49 | I/O — User I/O pin (function defined by user design) |
| Pino 50 | I/O — User I/O pin (function defined by user design) |
| Pino 51 | I/O — User I/O pin (function defined by user design) |
| Pino 52 | I/O — User I/O pin (function defined by user design) |
| Pino 53 | I/O — User I/O pin (function defined by user design) |
| Pino 54 | I/O — User I/O pin (function defined by user design) |
| Pino 55 | I/O — User I/O pin (function defined by user design) |
| Pino 56 | I/O — User I/O pin (function defined by user design) |
| Pino 57 | GND — Ground |
| Pino 58 | I/O — User I/O pin (function defined by user design) |
| Pino 59 | I/O — User I/O pin (function defined by user design) |
| Pino 60 | I/O — User I/O pin (function defined by user design) |
| Pino 61 | I/O — User I/O pin (function defined by user design) |
| Pino 62 | I/O — User I/O pin (function defined by user design) |
| Pino 63 | I/O — User I/O pin (function defined by user design) |
| Pino 64 | I/O — User I/O pin (function defined by user design) |
| Pino 65 | I/O — User I/O pin (function defined by user design) |
| Pino 66 | I/O — User I/O pin (function defined by user design) |
| Pino 67 | I/O — User I/O pin (function defined by user design) |
| Pino 68 | I/O — User I/O pin (function defined by user design) |
| Pino 69 | I/O — User I/O pin (function defined by user design) |
| Pino 70 | I/O — User I/O pin (function defined by user design) |
| Pino 71 | I/O — User I/O pin (function defined by user design) |
| Pino 72 | VCC — Supply voltage (5 V) |
| Pino 73 | I/O — User I/O pin (function defined by user design) |
| Pino 74 | I/O — User I/O pin (function defined by user design) |
| Pino 75 | I/O — User I/O pin (function defined by user design) |
| Pino 76 | I/O — User I/O pin (function defined by user design) |
| Pino 77 | I/O — User I/O pin (function defined by user design) |
| Pino 78 | I/O — User I/O pin (function defined by user design) |
| Pino 79 | I/O — User I/O pin (function defined by user design) |
| Pino 80 | I/O — User I/O pin (function defined by user design) |
| Pino 81 | I/O — User I/O pin (function defined by user design) |
| Pino 82 | I/O — User I/O pin (function defined by user design) |
| Pino 83 | I/O — User I/O pin (function defined by user design) |
| Pino 84 | I/O — User I/O pin (function defined by user design) |
| Pino 85 | GND — Ground |
| Pino 86 | I/O — User I/O pin (function defined by user design) |
| Pino 87 | I/O — User I/O pin (function defined by user design) |
| Pino 88 | I/O — User I/O pin (function defined by user design) |
| Pino 89 | I/O — User I/O pin (function defined by user design) |
| Pino 90 | I/O — User I/O pin (function defined by user design) |
| Pino 91 | I/O — User I/O pin (function defined by user design) |
| Pino 92 | I/O — User I/O pin (function defined by user design) |
| Pino 93 | I/O — User I/O pin (function defined by user design) |
| Pino 94 | I/O — User I/O pin (function defined by user design) |
| Pino 95 | I/O — User I/O pin (function defined by user design) |
| Pino 96 | I/O — User I/O pin (function defined by user design) |
| Pino 97 | I/O — User I/O pin (function defined by user design) |
| Pino 98 | I/O — User I/O pin (function defined by user design) |
| Pino 99 | I/O — User I/O pin (function defined by user design) |
| Pino 100 | I/O — User I/O pin (function defined by user design) |
| Pino 101 | VCC — Supply voltage (5 V) |
| Pino 102 | I/O — User I/O pin (function defined by user design) |
| Pino 103 | I/O — User I/O pin (function defined by user design) |
| Pino 104 | I/O — User I/O pin (function defined by user design) |
| Pino 105 | I/O — User I/O pin (function defined by user design) |
| Pino 106 | I/O — User I/O pin (function defined by user design) |
| Pino 107 | I/O — User I/O pin (function defined by user design) |
| Pino 108 | I/O — User I/O pin (function defined by user design) |
| Pino 109 | I/O — User I/O pin (function defined by user design) |
| Pino 110 | I/O — User I/O pin (function defined by user design) |
| Pino 111 | I/O — User I/O pin (function defined by user design) |
| Pino 112 | I/O — User I/O pin (function defined by user design) |
| Pino 113 | I/O — User I/O pin (function defined by user design) |
| Pino 114 | I/O — User I/O pin (function defined by user design) |
| Pino 115 | I/O — User I/O pin (function defined by user design) |
| Pino 116 | I/O — User I/O pin (function defined by user design) |
| Pino 117 | I/O — User I/O pin (function defined by user design) |
| Pino 118 | GND — Ground |
| Pino 119 | I/O — User I/O pin (function defined by user design) |
| Pino 120 | I/O — User I/O pin (function defined by user design) |
| Pino 121 | I/O — User I/O pin (function defined by user design) |
| Pino 122 | I/O — User I/O pin (function defined by user design) |
| Pino 123 | I/O — User I/O pin (function defined by user design) |
| Pino 124 | I/O — User I/O pin (function defined by user design) |
| Pino 125 | I/O — User I/O pin (function defined by user design) |
| Pino 126 | I/O — User I/O pin (function defined by user design) |
| Pino 127 | I/O — User I/O pin (function defined by user design) |
| Pino 128 | I/O — User I/O pin (function defined by user design) |
| Pino 129 | I/O — User I/O pin (function defined by user design) |
| Pino 130 | I/O — User I/O pin (function defined by user design) |
| Pino 131 | I/O — User I/O pin (function defined by user design) |
| Pino 132 | I/O — User I/O pin (function defined by user design) |
| Pino 133 | I/O — User I/O pin (function defined by user design) |
| Pino 134 | I/O — User I/O pin (function defined by user design) |
| Pino 135 | I/O — User I/O pin (function defined by user design) |
| Pino 136 | I/O — User I/O pin (function defined by user design) |
| Pino 137 | I/O — User I/O pin (function defined by user design) |
| Pino 138 | I/O — User I/O pin (function defined by user design) |
| Pino 139 | I/O — User I/O pin (function defined by user design) |
| Pino 140 | I/O — User I/O pin (function defined by user design) |
| Pino 141 | I/O — User I/O pin (function defined by user design) |
| Pino 142 | I/O — User I/O pin (function defined by user design) |
| Pino 143 | I/O — User I/O pin (function defined by user design) |
| Pino 144 | I/O — User I/O pin (function defined by user design) |
| Pino 145 | I/O — User I/O pin (function defined by user design) |
| Pino 146 | I/O — User I/O pin (function defined by user design) |
| Pino 147 | I/O — User I/O pin (function defined by user design) |
| Pino 148 | I/O — User I/O pin (function defined by user design) |
| Pino 149 | I/O — User I/O pin (function defined by user design) |
| Pino 150 | I/O — User I/O pin (function defined by user design) |
| Pino 151 | I/O — User I/O pin (function defined by user design) |
| Pino 152 | I/O — User I/O pin (function defined by user design) |
| Pino 153 | I/O — User I/O pin (function defined by user design) |
| Pino 154 | I/O — User I/O pin (function defined by user design) |
| Pino 155 | I/O — User I/O pin (function defined by user design) |
| Pino 156 | I/O — User I/O pin (function defined by user design) |
| Pino 157 | I/O — User I/O pin (function defined by user design) |
| Pino 158 | I/O — User I/O pin (function defined by user design) |
| Pino 159 | I/O — User I/O pin (function defined by user design) |
| Pino 160 | I/O — User I/O pin (function defined by user design) |
| Pino 161 | I/O — User I/O pin (function defined by user design) |
| Pino 162 | I/O — User I/O pin (function defined by user design) |
| Pino 163 | I/O — User I/O pin (function defined by user design) |
| Pino 164 | I/O — User I/O pin (function defined by user design) |
| Pino 165 | I/O — User I/O pin (function defined by user design) |
| Pino 166 | I/O — User I/O pin (function defined by user design) |
| Pino 167 | I/O — User I/O pin (function defined by user design) |
| Pino 168 | I/O — User I/O pin (function defined by user design) |
| Pino 169 | I/O — User I/O pin (function defined by user design) |
| Pino 170 | I/O — User I/O pin (function defined by user design) |
| Pino 171 | I/O — User I/O pin (function defined by user design) |
| Pino 172 | I/O — User I/O pin (function defined by user design) |
| Pino 173 | I/O — User I/O pin (function defined by user design) |
| Pino 174 | I/O — User I/O pin (function defined by user design) |
| Pino 175 | I/O — User I/O pin (function defined by user design) |
| Pino 176 | I/O — User I/O pin (function defined by user design) |
| Pino 177 | I/O — User I/O pin (function defined by user design) |
| Pino 178 | I/O — User I/O pin (function defined by user design) |
| Pino 179 | I/O — User I/O pin (function defined by user design) |
| Pino 180 | I/O — User I/O pin (function defined by user design) |
| Pino 181 | I/O — User I/O pin (function defined by user design) |
| Pino 182 | I/O — User I/O pin (function defined by user design) |
| Pino 183 | I/O — User I/O pin (function defined by user design) |
| Pino 184 | I/O — User I/O pin (function defined by user design) |
| Pino 185 | I/O — User I/O pin (function defined by user design) |
| Pino 186 | I/O — User I/O pin (function defined by user design) |
| Pino 187 | I/O — User I/O pin (function defined by user design) |
| Pino 188 | I/O — User I/O pin (function defined by user design) |
| Pino 189 | I/O — User I/O pin (function defined by user design) |
| Pino 190 | I/O — User I/O pin (function defined by user design) |
| Pino 191 | I/O — User I/O pin (function defined by user design) |
| Pino 192 | I/O — User I/O pin (function defined by user design) |
| Pino 193 | I/O — User I/O pin (function defined by user design) |
| Pino 194 | I/O — User I/O pin (function defined by user design) |
| Pino 195 | I/O — User I/O pin (function defined by user design) |
| Pino 196 | I/O — User I/O pin (function defined by user design) |
| Pino 197 | I/O — User I/O pin (function defined by user design) |
| Pino 198 | I/O — User I/O pin (function defined by user design) |
| Pino 199 | I/O — User I/O pin (function defined by user design) |
| Pino 200 | I/O — User I/O pin (function defined by user design) |
| Pino 201 | I/O — User I/O pin (function defined by user design) |
| Pino 202 | I/O — User I/O pin (function defined by user design) |
| Pino 203 | I/O — User I/O pin (function defined by user design) |
| Pino 204 | I/O — User I/O pin (function defined by user design) |
| Pino 205 | I/O — User I/O pin (function defined by user design) |
| Pino 206 | I/O — User I/O pin (function defined by user design) |
| Pino 207 | I/O — User I/O pin (function defined by user design) |
| Pino 208 | I/O — User I/O pin (function defined by user design) |
Aplicações típicas
EPM9560WI208-20 é adequado para 6 aplicaçãos: Aerospace and Military Avionics, Industrial Process Control, Telecommunication Line Cards, Legacy Bus-Bridge and Address Decoding, Test and Measurement Instrumentation, Medical Diagnostic Imaging Systems.
Aerospace and Military Avionics
The EPM9560WI208-20 fits aerospace and military avionics by combining 560 macrocells of deterministic glue logic with a hermetic CQFP-208 ceramic package rated for industrial temperature. Designers use the 23.6ns tPD to implement MIL-STD-1553 bus bridges, ARINC 429 line receivers, and radar timing controllers where instant-on EEPROM configuration is required and plastic QFP parts are prohibited. The JTAG-based IEEE 1149.1 boundary scan enables board-level test on flight hardware.
Recomendado
Industrial Process Control
The EPM9560WI208-20 supports industrial process control by providing 560 macrocells and 212 user I/Os for PLC backplane glue, motor-control state machines, and deterministic sensor-fusion timing. The 23.6ns propagation delay meets deterministic cycle-time budgets for safety interlocks, and the ceramic package tolerates wide temperature swings near drives and furnaces. JTAG in-system programming simplifies field reconfiguration when process recipes change.
Recomendado
Telecommunication Line Cards
The EPM9560WI208-20 addresses telecom line-card requirements by delivering 560 macrocells for TDM bus arbitration, framer interfacing, and protocol bridging across E1/T1 and SONET/SDH tributaries. The 23.6ns timing supports deterministic cell delineation, while 212 user I/Os accommodate multi-port front ends without external buffers. Instant-on EEPROM behavior eliminates external boot PROMs and reduces bill of materials cost per slot.
Recomendado
Legacy Bus-Bridge and Address Decoding
The EPM9560WI208-20 acts as a legacy bus-bridge and address decoder between microprocessors, DSPs, ASICs, and FPGAs. With 560 macrocells and 23.6ns tPD, it can replace multiple discrete PAL/GAL devices and discrete logic gates, shrinking board area and improving signal integrity. The 208-pin QFP exposes enough user I/Os for 32-bit data buses plus dedicated chip-select and wait-state generation outputs.
Recomendado
Test and Measurement Instrumentation
The EPM9560WI208-20 enables test and measurement front ends where deterministic timing and high I/O count are mandatory. It generates precise trigger patterns, scan-chain muxing, and reference clock conditioning for oscilloscopes and protocol analyzers. The 23.6ns tPD allows 42 MHz operation in synchronous state machines, and JTAG boundary-scan supports in-fixture test access on dense probe cards.
Recomendado
Medical Diagnostic Imaging Systems
The EPM9560WI208-20 supports medical imaging by providing deterministic timing for ultrasound beamformer sequencing, MRI gradient control, and CT detector multiplexing. The 560-cell capacity integrates multiple timing and channel-select functions previously requiring several discrete PLDs. The ceramic CQFP-208 package tolerates autoclave-style sterilization cycles in surgical imaging carts and provides long-term reliability required by IEC 60601-1 medical equipment standards.
Recomendado
Resumo dos produtos recomendados
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EPM9480RC240-20
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What type of device is the EPM9560WI208-20?
The EPM9560WI208-20 is a 560-cell Complex Programmable Logic Device (CPLD) from the Altera / Intel MAX 9000 family, classified as an EE PLD. According to the EPM9560 datasheet (Alldatasheet listing, 46 pages), it provides 16 LABs, up to 212 user I/Os, and 23.6ns pin-to-pin delay in a CQFP-208 ceramic package.
What is the pin-to-pin propagation delay of the EPM9560WI208-20?
The EPM9560WI208-20 has a worst-case pin-to-pin propagation delay (tPD) of 23.6 ns, corresponding to its -20 speed grade. Faster -15 and -10 speed grades are available in the same family for tighter timing budgets.
How many macrocells and I/O pins does the EPM9560WI208-20 provide?
The EPM9560WI208-20 integrates 560 macrocells organized into 16 logic array blocks (LABs) and supports up to 212 user I/O pins. This places it at the high-density end of the MAX 9000 series, suitable for complex glue logic and bus-interface designs.
Where can I download the EPM9560WI208-20 datasheet PDF?
The EPM9560 family datasheet is publicly hosted at https://www.alldatasheet.com/datasheet-pdf/pdf/392941/ALTERA/EPM9560.html. The original Altera datasheet covers architecture, timing, JTAG programming, and CQFP-208 pin assignments used by the WI208-20 variant.
What design software supports the EPM9560WI208-20?
The EPM9560WI208-20 is supported by Altera MAX+PLUS II (legacy) and Quartus Prime design tools. Both environments accept VHDL, Verilog, and schematic entry, and both can target the MAX 9000 device family directly via JTAG.
What is the difference between the EPM9560WI208-20 and the EPM9560RI208-20?
The EPM9560WI208-20 is a Ceramic QFP-208 variant with gull-wing leads rated for industrial temperature, while the EPM9560RI208-20 uses a plastic or different I-package with industrial rating. Both share the same 560-cell MAX 9000 die and identical 23.6ns speed grade at the -20 suffix.
Can the EPM9560WC208-20C drop in for the EPM9560WI208-20?
Yes, the EPM9560WC208-20C shares the same MAX 9000 die, the same 208-pin QFP footprint, and the same -20 speed grade as the EPM9560WI208-20, making it a drop-in replacement on the same PCB land pattern. The C-suffix indicates commercial temperature grading; confirm thermal requirements before substituting in industrial designs.
Is the EPM9560WI208-20 RoHS compliant?
RoHS compliance for the EPM9560WI208-20 is not explicitly stated in the available distributor listings. Because the part uses a ceramic package with gull-wing leads, historically it has been associated with non-RoHS / lead-bearing terminations; verify with the manufacturer's material declaration before using in RoHS-restricted designs.
Where can I buy the EPM9560WI208-20 in stock?
The EPM9560WI208-20 is available from authorized distributors including Intel / Altera franchised partners, Octopart-listed resellers, and specialty brokers. Lead time for ceramic CQFP parts typically ranges from 6 to 14 weeks, depending on factory allocation and lot traceability requirements.
What is the price of the EPM9560WI208-20?
The EPM9560WI208-20 list price as of 2026-09-13 ranges from approximately 185 USD at qty 1 down to 105 USD at qty 1000, based on distributor listings. Ceramic CQFP CPLDs typically command a price premium over plastic QFP equivalents due to package cost and lower production volume.
What is the EPM9560WI208-20 best used for?
The EPM9560WI208-20 is best used as deterministic, instant-on glue logic in systems that require high-density (560-cell) programmable logic in a hermetic ceramic package. Common roles include address decoding, bus arbitration, custom peripheral interfacing, and state-machine controllers in aerospace, military, and high-reliability industrial designs.
Is the EPM9560WI208-20 still in production?
The EPM9560WI208-20 is marked Not Recommended for New Designs (NRND) by Intel / Altera, with the MAX 9000 family largely superseded by the MAX II, MAX V, and MAX 10 CPLD families. Existing designs continue to be supported, but long-term volume production is constrained to legacy and aerospace programs.
What is the best Intel / Altera drop-in replacement for the EPM9560WI208-20?
The best same-family drop-in replacement for the EPM9560WI208-20 is the EPM9560WC208-20 (commercial temp) or EPM9560WC208-20C variant, both sharing the same MAX 9000 die and CQFP-208 footprint. For higher speed, the EPM9560WC208-15 family member offers 15 ns timing in the same package.
Can the EPM9560RI240-20 substitute for the EPM9560WI208-20?
The EPM9560RI240-20 is a different package (240-pin RQFP) and is NOT a drop-in replacement for the 208-pin CQFP of the EPM9560WI208-20; PCB rework is required. Within the same 208-pin footprint, prefer the EPM9560WC208-20 or EPM9560RC208-20 family members.
Dados de referência de engenharia para EPM9560WI208-20 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Choose the EPM9560WI208-20 when your design requires industrial temperature operation in a ceramic CQFP-208 package, specifically for aerospace, military, or harsh-environment programs where plastic QFP parts are not acceptable. If your design is commercial-grade and you only need the same 560-cell MAX 9000 logic, the EPM9560WC208-20 offers the same die in the same footprint at lower cost. If your timing budget requires under 20 ns propagation delay, step up to the EPM9560WC208-15 (15 ns) in the same package. Avoid the EPM9560RI240-20 or EPM9560RC240-20 for drop-in substitution; they use a 240-pin package and require PCB rework. For new designs where the MAX 9000 is not mandated, consider the MAX II or MAX V CPLD families as modern RoHS-compliant alternatives.
Comparação com alternativas
| Parâmetro | Este produto | EPM9560WC208-20 | EPM9560WC208-20C | EPM9560WC208-15 | EPM9560WC208-15C | EPM9560WC208 |
|---|---|---|---|---|---|---|
| Package | CQFP-208 (Ceramic QFP) | CQFP-208 - same | CQFP-208 - same | CQFP-208 - same | CQFP-208 - same | CQFP-208 - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Maximum User I/O | 212 | 212 | 212 | 212 | 212 | 212 |
| Process / Architecture | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 | 0.35 micron CMOS EEPROM, MAX 9000 |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
Principais diferenciais
- Industrial temperature grade in ceramic CQFP-208 (vs EPM9560WC208-20C)
- Highest-density MAX 9000 in 208-pin footprint (vs EPM9480RC208-20)
- Deterministic 23.6 ns tPD (vs EPM9560WC208-15)
Notas de projeto
The CQFP-208 ceramic package has gull-wing leads with larger pad geometry than a plastic QFP. Land pattern must follow the JEDEC MS-022 variation for ceramic QFP, with copper pads approximately 0.020 inch wider than the plastic variant to accommodate lead compliance. Inspect lead coplanarity during incoming QA; ceramic packages are more susceptible to lead warpage after thermal cycling.
Estimated: the MAX 9000 family draws approximately 200-400 mA from a 5 V supply at full I/O toggle, giving 1-2 W dissipation. In a ceramic QFP with typical theta_JA of 35-45 C/W, junction temperature rise above ambient stays below 90 C in normal industrial environments, but designers should derate by 10-15% in sealed aerospace enclosures without forced airflow.
Because the EPM9560WI208-20 drives 212 user I/Os at 23.6 ns edge rates, use series termination (22-33 ohm) on clock and high-fanout outputs to limit ringing on long PCB traces. Place VCC and GND pins with at least one decoupling cap pair (0.1 uF + 10 uF) within 5 mm of each supply pin to suppress SSO-induced ground bounce.
Do not assume the EPM9560WI208-20 is RoHS compliant without checking the manufacturer's material declaration; the ceramic CQFP historically used lead-bearing terminations. For new designs targeting RoHS, prefer the C-suffix variants (EPM9560WC208-20C, EPM9560WC208-15C) which carry lead-free finishes.
When laying out JTAG programming signals (TCK, TMS, TDI, TDO, TRST), keep the chain under 6 inches total to avoid IEEE 1149.1 timing violations. Provide a 10 kohm pull-up on TCK and TMS to keep the TAP controller in a benign state during board power-up before the CPLD is configured.
Informações de conformidade
RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Sem chumbo
No
Sem halogênios
Unknown
Minerais de conflito
Unknown
Compliance values not explicitly stated in available distributor listings. The ceramic CQFP-208 package historically used lead-bearing terminations; the -WI- variant is not marked with a C-suffix and should be assumed non-RoHS until verified by manufacturer declaration.
Dados verificados em: 2026-09-13
— dados verificados e curados pela equipe de engenharia de componentes da XAIPART
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Componentes & termos relacionados
Intel
Altera
EPM9560WI208-20
EPM9560WC208-20
EPM9560WC208-20C
EPM9560WC208-15
EPM9560WC208-15C
CPLD
Complex Programmable Logic Device
EE PLD
MAX 9000
macrocell
logic array block
CQFP-208
Ceramic Quad Flat Pack
gull wing
IEEE 1149.1
JTAG
boundary scan
0.35 micron CMOS
EEPROM
MAX+PLUS II
Quartus
industrial temperature grade
MIL-STD-1553
ARINC 429
PLD
programmable logic
instant-on
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