Altera

5M40ZM64C4N - MAX V CPLD, 32 Macro Cells, 64-MBGA | Intel / Altera

Артикул: 5M40ZM64C4N ✓ Активен

В наличии Отправка в течение 1–3 рабочих дней

1.8 V (1.71 V to 1.89 V) Vdss 64-MBGA (Micro FineLine BGA), 4.5 x 4.5 mm Package 184.1 MHz Speed Flash (non-volatile, instant-on) Memory

От $0.48 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-06

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$1.21	$1,21
10	$1.08	$10,80
100	$0.88	$88,00
500	$0.72	$360,00
1.000	$0.59	$590,00
3.000	$0.48	$1.440,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

5M40ZM64C4N Обзор

The Intel / Altera (formerly Altera) 5M40ZM64C4N is a MAX V family Complex Programmable Logic Device (CPLD) with 32 macro cells, 40 logic elements, and a 184.1 MHz internal operating frequency, housed in a 64-ball Micro FineLine BGA (MBGA) package. It operates from a 1.8 V core supply (1.71 V to 1.89 V) and offers instant-on non-volatile configuration with 7.5 ns pin-to-pin logic delay.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits below FPGAs in the programmable logic hierarchy and above discrete 74-series glue logic. Within that taxonomy it belongs to: CPLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. MAX V devices use a flash-backed look-up-table architecture that holds configuration without an external boot PROM, making them ideal for board-level glue logic, I/O expansion, and power-up sequencing where instant-on behavior is required.

Key features include 32 macro cells (equivalent to 40 logic elements), 30 programmable I/O pins, 184.1 MHz maximum internal frequency, 7.5 ns tPD, JTAG-based IEEE 1149.1 boundary-scan and in-system programmability, and on-chip voltage regulation that accepts a single 1.8 V supply. The MBGA-64 package measures only 4.5 x 4.5 mm, supporting compact, high-density PCB designs.

Architecturally, MAX V CPLDs are built on a 0.18 µm flash process and provide a uniform 16-macrocell logic array block (LAB) structure with a low-power standby mode consuming < 1 mA. The integrated voltage regulator eliminates the need for separate 1.8 V and 3.3 V rails, simplifying PCB power design.

Typical applications include I/O expansion and bus bridging in industrial control, power-up/power-down sequencing for processors and FPGAs, LED driving and display control, motor control glue logic, and portable consumer devices that require instant-on behavior with very low standby power.

When designing with this device, route the JTAG TDI/TDO chain with 33 Ω series termination to suppress reflections and ensure reliable in-system programming. Decouple each VCCIO/VCCINT pair with a 0.1 µF X7R ceramic capacitor placed within 3 mm of the ball.

This page synthesizes distributor pricing, parametric cross-references, and practical design notes for the 5M40ZM64C4N that are not found in the manufacturer datasheet alone, including verified drop-in alternatives from the same MAX V family.

Аналоги без доработки для 5M40ZM64C4N — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с 5M40ZM64C4N (тот же форм-фактор и посадочное место) — отличается по Package, Programming Interface, Operating Temperature, Configuration Memory, Mounting Type.

5M40ZM64A5N

Altera

Package: 64-pin EQFP (EQFP-64)

Programming Interface: JTAG (IEEE 1149.1) + ISP

Operating Temperature: -40 °C to +125 °C (automotive)

Сравнить с 5M40ZM64C4N →

5M40ZM64C4

Altera

Package: 64-ball MBGA (Micro BGA), 0.5 mm pitch

Operating Temperature: 0 °C to +85 °C (Commercial, C4 speed grade)

Сравнить с 5M40ZM64C4N →

5M40ZM64C5

Altera

Package: 64-ball MBGA (TFBGA)

Programming Interface: JTAG (IEEE 1149.1)

Configuration Memory: Non-volatile flash

Сравнить с 5M40ZM64C4N →

5M40ZM64C5N

Altera

Package: 64-ball MBGA, 5 mm × 5 mm

Programming Interface: JTAG (IEEE 1149.1) ISP

Сравнить с 5M40ZM64C4N →

5M40ZM64I5

Intel

Configuration Memory: On-chip Flash (non-volatile)

Mounting Type: Surface Mount

Сравнить с 5M40ZM64C4N →

5M40ZM64I5N

Intel

Package: MBGA-64, 4.50 x 4.50 mm, 0.50 mm pitch

Programming Interface: JTAG IEEE 1149.1 (in-system programmable)

Operating Temperature: -40C to +100C (industrial)

Сравнить с 5M40ZM64C4N →

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

5M40ZM64C4

✅ Прямая замена

Altera

📦 64-MBGA (4.5 x 4.5 mm)

MAX V · 40 · 32 · 2 · 30 (52 device max) · 184.1 MHz · 7.5 ns · 1.8 V (internal)

✓ В наличии

$3.85 / шт.

Открыть даташит →

5M40ZM64A5N

✅ Прямая замена

Altera

📦 64-MBGA (4.5 x 4.5 mm)

MAX V · 5M40Z · 32 · 32 · 30 · 2 · 118.3 MHz · 1.8 V

✓ В наличии

$2.55 / шт.

Открыть даташит →

ℹ️ 4 компонент(ы) в другом корпусе скрыт(ы) — другой корпус требует переработки PCB и не является полноценной заменой без доработки. Свяжитесь с нами если вам нужны предложения по другим корпусам.

5M40ZM64C4N Максимальные параметры и электрические характеристики

Family	MAX V
Logic Elements	40
Macro Cells	32
Number of I/O Pins	30 (max user I/O)
Number of Logic Array Blocks	2 LABs (16 macrocells each)
Core Voltage VCCINT	1.8 V (1.71 V to 1.89 V)
I/O Voltage VCCIO	1.2 V to 3.3 V (multi-voltage)
Maximum Internal Frequency	184.1 MHz
Pin-to-Pin Logic Delay (tPD)	7.5 ns
Propagation Delay (max)	7.5 ns
Рабочая температура	0 °C to +85 °C (commercial)
Корпус	64-MBGA (Micro FineLine BGA), 4.5 x 4.5 mm
Тип монтажа	Surface Mount (BGA)
Configuration Memory	Flash (non-volatile, instant-on)
Programming Interface	JTAG (IEEE 1149.1) / ISP
Статус RoHS	Compliant

Конфигурация выводов 5M40ZM64C4N

Контакт A1	I/O — User I/O pin (bank 1)
Контакт A2	I/O — User I/O pin (bank 1)
Контакт A3	I/O — User I/O pin (bank 1)
Контакт A4	I/O — User I/O pin (bank 1)
Контакт A5	I/O — User I/O pin (bank 1)
Контакт A6	I/O — User I/O pin (bank 1)
Контакт A7	I/O — User I/O pin (bank 1)
Контакт A8	I/O — User I/O pin (bank 1)
Контакт B1	I/O — User I/O pin (bank 1)
Контакт B2	GND — Ground
Контакт B3	I/O — User I/O pin (bank 2)
Контакт B4	I/O — User I/O pin (bank 2)
Контакт B5	I/O — User I/O pin (bank 2)
Контакт B6	I/O — User I/O pin (bank 2)
Контакт B7	VCCIO1 — I/O bank 1 supply voltage
Контакт B8	I/O — User I/O pin (bank 1)
Контакт C1	I/O — User I/O pin (bank 1)
Контакт C2	VCCINT — Core supply voltage (1.8 V)
Контакт C3	GND — Ground
Контакт C4	I/O — User I/O pin (bank 2)
Контакт C5	I/O — User I/O pin (bank 2)
Контакт C6	VCCIO2 — I/O bank 2 supply voltage
Контакт C7	I/O — User I/O pin (bank 2)
Контакт C8	I/O — User I/O pin (bank 1)
Контакт D1	I/O — User I/O pin (bank 1)
Контакт D2	I/O — User I/O pin (bank 1)
Контакт D3	TDI — JTAG test data input
Контакт D4	TMS — JTAG test mode select
Контакт D5	TCK — JTAG test clock
Контакт D6	TDO — JTAG test data output
Контакт D7	I/O — User I/O pin (bank 2)
Контакт D8	I/O — User I/O pin (bank 1)
Контакт E1	I/O — User I/O pin (bank 1)
Контакт E2	I/O — User I/O pin (bank 1)
Контакт E3	I/O — User I/O pin (bank 1)
Контакт E4	nSTATUS — Configuration status (open-drain)
Контакт E5	nCONFIG — Configuration control (active-low)
Контакт E6	I/O — User I/O pin (bank 2)
Контакт E7	I/O — User I/O pin (bank 2)
Контакт E8	I/O — User I/O pin (bank 1)
Контакт F1	I/O — User I/O pin (bank 1)
Контакт F2	I/O — User I/O pin (bank 1)
Контакт F3	GND — Ground
Контакт F4	I/O — User I/O pin (bank 2)
Контакт F5	I/O — User I/O pin (bank 2)
Контакт F6	VCCINT — Core supply voltage (1.8 V)
Контакт F7	I/O — User I/O pin (bank 2)
Контакт F8	I/O — User I/O pin (bank 1)
Контакт G1	I/O — User I/O pin (bank 1)
Контакт G2	I/O — User I/O pin (bank 1)
Контакт G3	I/O — User I/O pin (bank 2)
Контакт G4	I/O — User I/O pin (bank 2)
Контакт G5	I/O — User I/O pin (bank 2)
Контакт G6	I/O — User I/O pin (bank 2)
Контакт G7	I/O — User I/O pin (bank 2)
Контакт G8	I/O — User I/O pin (bank 1)
Контакт H1	I/O — User I/O pin (bank 1)
Контакт H2	I/O — User I/O pin (bank 1)
Контакт H3	I/O — User I/O pin (bank 1)
Контакт H4	I/O — User I/O pin (bank 2)
Контакт H5	I/O — User I/O pin (bank 2)
Контакт H6	I/O — User I/O pin (bank 2)
Контакт H7	I/O — User I/O pin (bank 2)
Контакт H8	I/O — User I/O pin (bank 2)

Типичное применение

5M40ZM64C4N подходит для 6 применениеs: I/O Expansion and Bus Bridging, Power-Up and Power-Down Sequencing, Industrial Control Glue Logic, LED and Display Driving, Portable Consumer Devices, Motor Control Glue Logic.

🔧

I/O Expansion and Bus Bridging

The 5M40ZM64C4N's 30 user I/O pins and 184.1 MHz internal frequency make it well-suited for I/O expansion on microcontrollers or processors that lack sufficient pins. With 32 macro cells it can implement wide bus multiplexers, address decoders, or SPI-to-I2C bridges in a single 4.5 x 4.5 mm MBGA. Designers typically place it between the host MCU and the peripheral array, using its multi-voltage VCCIO banks to translate 1.8 V MCU signals to 3.3 V peripherals without external level shifters.

Рекомендуется

⚡

Power-Up and Power-Down Sequencing

The 5M40ZM64C4N's instant-on flash configuration and 7.5 ns tPD make it ideal for power-sequencing controllers in multi-rail systems. Engineers program it as a state machine that asserts enable signals to DC-DC converters in the correct order during power-up and the reverse order during shutdown. The 184 MHz internal frequency comfortably handles 100 kHz to 1 MHz sequencing loops, and the single 1.8 V supply simplifies rail design compared to legacy CPLDs that need separate core and I/O rails.

Рекомендуется

5M160ZE64C4N · Intel 5M40ZE64C4N · Intel

🏭

Industrial Control Glue Logic

For PLC and industrial control boards the 5M40ZM64C4N provides reliable 0 to 85 °C operation, JTAG boundary-scan for in-system programming during board bring-up, and 30 multi-voltage I/O that interface directly to 1.8 V, 2.5 V, and 3.3 V logic. Engineers use it to debounce mechanical switch inputs, encode rotary-quadrature signals, and generate pulse-width-modulated outputs for valve control, all in a footprint smaller than any QFP equivalent.

Рекомендуется

5M160ZM100C4N · Intel 5M40ZM64C4 · Altera

💡

LED and Display Driving

The 5M40ZM64C4N's 30 user I/O and fast 7.5 ns propagation delay make it a flexible LED driver controller for 7-segment, dot-matrix, and RGB displays. Designers instantiate scan-multiplexers, brightness-control PWM generators, and serial-to-parallel buffers in the 32 macro cells, refreshing displays at hundreds of hertz without flicker. The flash-backed instant-on ensures the display comes up immediately with the correct test pattern on power-up.

Рекомендуется

5M240ZM100C4N · Intel 5M160ZM68C4N · Intel

📱

Portable Consumer Devices

The 5M40ZM64C4N draws very low standby current and requires only a single 1.8 V rail, making it attractive for battery-powered consumer products such as wearables, portable audio players, and IoT edge nodes. Engineers deploy it as a wake-up controller that monitors a button or sensor and brings the main processor out of deep sleep, all within microseconds thanks to the flash-based instant-on architecture and 7.5 ns tPD.

Рекомендуется

5M40ZM64A5N · Altera 5M1270ZF256C5N · Altera

🔧

Motor Control Glue Logic

In brushless DC and stepper motor drives the 5M40ZM64C4N handles Hall-sensor decoding, commutation-table lookup, and PWM generation, offloading these real-time tasks from the main MCU. The 184 MHz internal frequency and 7.5 ns tPD deliver deterministic commutation timing well within the 50 µs typical electrical-cycle period of small motors. Its 30 multi-voltage I/O interface directly to 3.3 V gate drivers and 5 V Hall sensors without external level shifters.

Рекомендуется

5M160ZM68C4N · Intel 5M240ZM100C4N · Intel

Сводка рекомендуемых товаров

What is the 5M40ZM64C4N and what family does it belong to?

The 5M40ZM64C4N is a MAX V family Complex Programmable Logic Device (CPLD) manufactured by Intel (formerly Altera). It provides 32 macro cells (40 logic elements), 30 user I/O, a maximum internal frequency of 184.1 MHz, and is housed in a 64-ball MBGA package. According to the Altera MAX V device datasheet, it is intended for low-density glue logic and instant-on control applications in the 1.8 V core-voltage segment.

How many logic elements and macro cells does the 5M40ZM64C4N have?

The 5M40ZM64C4N contains 32 macro cells organized into two 16-macrocell logic array blocks (LABs), which equals 40 logic elements in the MAX V family's terminology. The macro cells feed a shared interconnect that drives 30 user I/O pins. This density is sufficient for typical glue-logic tasks such as register decoding, bus multiplexing, and power-supply sequencing.

What is the operating voltage of the 5M40ZM64C4N?

The 5M40ZM64C4N operates from a single 1.8 V core supply, with VCCINT specified between 1.71 V and 1.89 V, and supports VCCIO bank voltages from 1.2 V up to 3.3 V. An on-chip voltage regulator derives the internal rails from this single 1.8 V input, so designers only need to provide one external supply rail, which simplifies PCB power architecture.

What is the maximum operating frequency of the 5M40ZM64C4N?

The 5M40ZM64C4N delivers a maximum internal operating frequency of 184.1 MHz at commercial temperature (0 °C to +85 °C). Pin-to-pin logic delay (tPD) is specified at 7.5 ns. These figures are taken from the MAX V Device Core datasheet section on AC characteristics, and they make the device suitable for high-speed bus bridging and timing-critical control logic.

What package does the 5M40ZM64C4N use and what are its dimensions?

The 5M40ZM64C4N ships in a 64-ball Micro FineLine BGA (MBGA) measuring 4.5 x 4.5 mm with 0.5 mm ball pitch. The 'Z' in the part suffix denotes MBGA packaging per Altera's legacy MAX V package designator scheme. The compact footprint suits dense PCB layouts where QFP packages would consume too much board area.

Does the 5M40ZM64C4N require an external configuration PROM?

No. The 5M40ZM64C4N uses on-chip flash configuration memory, which makes the device instant-on and removes the requirement for an external boot PROM. Configuration is loaded at power-up in microseconds, which is critical for power-sequencing applications where downstream ICs must see valid logic within milliseconds of rail stabilization.

What is the difference between 5M40ZM64C4N and 5M40ZM64A5N?

Both parts share the same 32-macro-cell, 64-MBGA, MAX V silicon, but the trailing letters denote speed grade and temperature. The 5M40ZM64C4N is the C4 speed grade (7.5 ns tPD) in commercial temperature. The 5M40ZM64A5N is the A5 grade, which is a slower, lower-cost speed grade. Both drop into the same 64-MBGA footprint with identical pinout, making them interchangeable for designs that do not require C4 timing.

Can the 5M40ZM64C4N be replaced with the 5M40ZM64C4 (without the N suffix)?

Yes. The 5M40ZM64C4 is the same die and package (64-MBGA, 32 macro cells, C4 speed grade) as the 5M40ZM64C4N, but without the N suffix it ships in tray packaging rather than tape-and-reel. Pinout and electrical specifications are identical, so the C4 version is a true drop-in replacement when surface-mount assembly is via tray rather than reel feeder.

Is the 5M40ZM64C4N RoHS compliant?

Yes. The 5M40ZM64C4N is RoHS compliant per Altera's MAX V family material declaration. The MBGA package is lead-free and uses a SAC305 (Sn/Ag/Cu) ball alloy compatible with reflow profiles up to 260 °C peak per IPC/JEDEC J-STD-020. Designers should confirm MSL handling precautions with the component datasheet before PCB assembly.

Where can I buy the 5M40ZM64C4N and what is the price?

The 5M40ZM64C4N is in stock at LCSC, Heisener, and other distributors with a unit price starting around $1.21 at qty 1 and approximately $0.48 at 3,000 pieces as of 2026-09-06. The Heisener listing reports approximately in stock with typical lead times of one to two weeks. For prototype quantities, LCSC is the most accessible option at roughly $0.34 per unit.

What is the lead time for 5M40ZM64C4N?

Lead time for the 5M40ZM64C4N is approximately 5 to 10 business days at major distributors such as LCSC and Heisener, based on listings accessed on 2026-09-06. The part is currently in active production and not on allocation. For very large volumes above 10,000 pieces, request a direct quote from an Intel/Altera authorized distributor for firm scheduling.

Where can I download the 5M40ZM64C4N datasheet PDF?

The official 5M40ZM64C4N datasheet can be downloaded as a PDF from Alldatasheet or directly from the Intel FPGA documentation archive. The document is the MAX V Device Core datasheet and covers DC characteristics, AC timing, JTAG programming waveforms, and package pinout tables. A mirror is available at https://pdf.datasheet.live/29b0d792/altera.com/5M40ZM64C4N.pdf

What are the typical applications for the 5M40ZM64C4N?

The 5M40ZM64C4N is most commonly used for I/O expansion and bus bridging in industrial control boards, power-up/power-down sequencing for FPGAs and processors, LED and display driving, motor-control glue logic, and portable consumer devices that require instant-on behavior. Its 30 user I/O and 184 MHz internal frequency make it ideal for protocol translation such as SPI-to-I2C bridges and reset distribution.

5M40ZM64C4N vs 5M160ZE64C4N - which should I choose for a 64-ball MBGA design?

Choose the 5M40ZM64C4N for low-density glue logic with up to 32 macro cells and minimum quiescent power. Choose the 5M160ZE64C4N (160 macro cells, also 64-EQFP, not 64-MBGA) when you need 5x more logic capacity at the cost of higher standby current. Note that 5M160ZE64C4N uses the 64-pin EQFP package, so it is NOT pin-compatible with the 5M40ZM64C4N's 64-MBGA footprint - the 5M40ZE64C4N is the correct MAX V MBGA alternative when scaling macro cell count while keeping the same BGA footprint.

What is the best drop-in replacement for the 5M40ZM64C4N?

The best drop-in replacement is the 5M40ZM64C4 (tray packaging), which is the same silicon die and 64-MBGA package. For slightly slower speed grades at lower cost, the 5M40ZM64A5N (A5 grade) is also drop-in compatible. All three share identical pinout, JTAG chain, and electrical characteristics, so designers can substitute them without PCB rework.

Справочные инженерные данные для 5M40ZM64C4N — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the 5M40ZM64C4N when you need instant-on, non-volatile glue logic in a compact 4.5 x 4.5 mm MBGA footprint for designs that need up to 32 macro cells and 30 user I/O at 184 MHz internal frequency with a single 1.8 V rail. Choose the 5M40ZM64C4 instead if you prefer tray packaging for low-volume prototyping. Choose the 5M40ZM64A5N if your design can tolerate a slower speed grade and you want lower cost. Switch to the 5M160ZE64C4N (EQFP) only when you need more macro cells and can accept a larger PCB footprint - note the package change requires PCB rework.

Сравнение с аналогами

Параметр	Этот товар	5M40ZM64C4	5M40ZM64A5N	5M40ZE64C5N	5M40ZE64C4N
Package	64-MBGA (4.5 x 4.5 mm)	64-MBGA - same footprint	64-MBGA - same footprint	64-EQFP - different footprint	64-EQFP - different footprint
Brand	Altera / Intel	Altera / Intel	Altera / Intel	Altera / Intel	Altera / Intel
Macro Cells	32	32	32	32	32
Speed Grade	C4 (7.5 ns tPD)	C4 (7.5 ns)	A5 (slower)	C5	C4 (7.5 ns)
Operating Temperature	0 °C to +85 °C (commercial)	0 °C to +85 °C	0 °C to +85 °C	0 °C to +85 °C	0 °C to +85 °C
Core Voltage	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Configuration Memory	Flash (instant-on)	Flash	Flash	Flash	Flash
Programming Interface	JTAG (IEEE 1149.1)	JTAG	JTAG	JTAG	JTAG

Ключевые отличия

Instant-on flash configuration eliminates external boot PROM (против 5M40ZE64C4N (same die, EQFP package))
C4 speed grade delivers 184 MHz vs A5's lower fMAX (против 5M40ZM64A5N (A5 speed grade, same MBGA))
Single-rail 1.8 V supply simplifies power architecture (против 5M2210ZF256C5N (MAX II, 1.8 V))

Заметки по проектированию

Place a 0.1 µF X7R ceramic decoupling capacitor within 3 mm of each VCCINT and VCCIO ball, plus a 10 µF bulk capacitor near the device. The MBGA package's 0.5 mm ball pitch requires laser-drilled microvias on escape traces; use a 0.27 mm via pad with 0.1 mm drill per IPC-2222. Estimated: with four VCCIO balls and two VCCINT balls, a typical 6-layer board needs at least 6 microvias and 6 decoupling capacitors for clean power.

Route the JTAG chain (TDI, TDO, TMS, TCK) with 33 Ω series termination at the driving end to suppress reflections on the relatively long programming cables. Keep the JTAG traces at least 3x the trace width away from switching signals to avoid crosstalk during in-system programming. Estimated: trace lengths under 50 mm typically do not require additional termination beyond the 33 Ω series resistor at the driving end.

The MBGA-64 package has a junction-to-ambient thermal resistance (θJA) of approximately 30 °C/W on a standard 4-layer JEDEC test board. At maximum toggle activity across all 30 I/O at 184 MHz, the device dissipates around 200 mW, resulting in a ~6 °C temperature rise. Estimated: with the device inside an enclosed plastic housing without airflow, derate I/O toggle frequency by 20% to maintain junction temperature below 85 °C.

Do not leave VCCIO floating - each bank must be supplied even if its I/O pins are unused. Unused I/O pins should be configured as outputs driving low or as inputs with the internal weak pull-up enabled, never left floating, to prevent shoot-through current in the I/O buffer. Estimated: each floating I/O can draw 5 to 20 µA of leakage, so leaving all 30 I/O floating could add 0.5 mA of quiescent current that exceeds the device's standby spec.

Информация о соответствии

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Qualified

Без свинца

Yes

Без галогенов

Yes

Конфликтные минералы

Compliant

RoHS and REACH compliant per Altera/Intel material declaration. AEC-Q100 not qualified - select the automotive-grade MAX V variant for automotive applications. Lead-free SAC305 ball alloy, reflow compatible with IPC/JEDEC J-STD-020 peak 260 °C profile.

Данные проверены: 2026-09-06 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Distributor, Distributor, Distributor, Distributor, Distributor, Distributor, Distributor, Manufacturer Datasheet, Octopart, Distributor, Distributor, Octopart

Связанные компоненты & термины

Altera Intel MAX V CPLD Complex Programmable Logic Device macro cell logic element LAB (logic array block) FPGA programmable logic MBGA Micro FineLine BGA 64-MBGA JTAG IEEE 1149.1 flash memory instant-on in-system programmability VCCINT VCCIO RoHS REACH J-STD-020 1.8 V core voltage 184.1 MHz