ADC1412D080HN-C1 - Dual 14-bit 80MSPS ADC | Renesas
Артикул: ADC1412D080HN-C1 ✗ Снят с производства| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $48.5 | $48,50 |
| 10 | $44.2 | $442,00 |
| 100 | $39.8 | $3.980,00 |
| 500 | $35.6 | $17.800,00 |
| 1.000 | $31.9 | $31.900,00 |
ADC1412D080HN-C1 Обзор
An ADC (Analog-to-Digital Converter) is a data acquisition integrated circuit that converts continuous-time analog signals into discrete digital codes, enabling downstream processing by microcontrollers, FPGAs, or DSPs. In the broader taxonomy, the ADC1412D080HN-C1 belongs to the class of pipeline ADCs, which interleave sub-ADCs and DACs to achieve high sample rates (the pipeline architecture -> successive-approximation/pipelined/sigma-delta ADC -> data converter -> data acquisition IC -> analog mixed-signal IC hierarchy). This topology delivers the best throughput-to-power trade-off in the 50-200 MSPS range.
Key features include 14-bit resolution, 80 MSPS sampling rate, dual-channel simultaneous sampling, configurable CMOS or LVDS DDR output interface, and an industrial temperature range of -40C to +85C. The device supports a 3-wire SPI-compatible serial interface for configuration. The HVQFN-64 (9x9 mm) package has low thermal resistance and is suitable for high-density PCB layouts common in communications infrastructure equipment.
The pipelined architecture uses a switched-capacitor front-end and digital error-correction logic, achieving low latency and high spurious-free dynamic range. The device requires an external reference and an external analog input driver, and the LVDS DDR mode minimizes the digital output bus width while preserving the 80 MSPS throughput, simplifying board-level routing between the ADC and the downstream FPGA receiver.
Typical applications include multi-carrier cellular base stations, radar and lidar receiver front-ends, medical imaging digitizers, and high-end oscilloscopes or spectrum analyzers. The Renesas ADC1412D125HN-C1 (125 MSPS) and ADC1412D065HN-C1 (65 MSPS) variants cover the same application space at different sampling rates, all sharing the HVQFN-64 (9x9) footprint for design scalability.
When designing with this device, prioritize proper grounding and power-rail decoupling; Renesas application briefs recommend a clean analog supply with a ferrite bead plus a 10uF/0.1uF capacitor stack on the AVDD pin. Note that the manufacturer marks this part Obsolete per Renesas documentation, so procurement should plan long lead times or evaluate current production parts from the ADC1412D family.
This page consolidates distributor pricing, same-package drop-in alternatives, and design guidance beyond what is in the standalone Renesas datasheet, helping engineers source and integrate the ADC1412D080HN-C1 efficiently.
Аналоги без доработки для ADC1412D080HN-C1 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с ADC1412D080HN-C1 (тот же форм-фактор и посадочное место) — отличается по Package, Resolution, Number of Channels, Input Type, Sampling Rate.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
ADC1412D125HN-C1
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADC1412D065HN-C1
✅ Прямая замена✓ В наличии
$21.45 / шт.
Открыть даташит →ADC1412D080HN/C1,5
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADC1413S125HN-C1
✅ Прямая замена✓ В наличии
$21.3 / шт.
Открыть даташит →ADC1112D125HN-C18
✅ Прямая замена✓ В наличии
$9.48 / шт.
Открыть даташит →ADC1012D080HN/C1:5
✅ Прямая замена✓ В наличии
$12.1 / шт.
Открыть даташит →ADC1412D080HN-C1 Максимальные параметры и электрические характеристики
| Разрешение | 14 bits |
| Number of Input Channels | 2 (dual, simultaneous sampling) |
| Частота дискретизации | 80 MSPS |
| Architecture | Pipelined |
| Input Type | Differential analog inputs |
| Digital Output Interface | CMOS or LVDS DDR (selectable) |
| Configuration Interface | 3-wire SPI-compatible serial |
| Input Clock | Sample-rate dependent, single-ended or differential clock input |
| Supply Voltage (AVDD) | 3.3 V (per package datasheet family) |
| Рабочая температура | -40C to +85C (industrial grade) |
| Корпус | 64-VFQFPN / HVQFN-64 (9x9 mm, 0.85 mm height, SOT804-6) |
| Число выводов | 64 |
| Тип монтажа | Surface Mount |
| Screening Level | Industrial |
Конфигурация выводов ADC1412D080HN-C1
| Контакт 1 | CLK+ — Differential clock input (positive) |
| Контакт 2 | CLK- — Differential clock input (negative) |
| Контакт 3 | NC — Not connected (per datasheet) |
| Контакт 4 | AVDD — Analog 3.3V supply |
| Контакт 5 | VREFIN — Voltage reference input |
| Контакт 6 | AGND — Analog ground |
| Контакт 7 | AIN1A+ — Channel 1 differential input positive |
| Контакт 8 | AIN1A- — Channel 1 differential input negative |
| Контакт 9 | AIN1B+ — Channel 1 second input positive |
| Контакт 10 | AIN1B- — Channel 1 second input negative |
| Контакт 11 | NC — Not connected (per datasheet) |
| Контакт 12 | AVDD — Analog 3.3V supply |
| Контакт 13 | AGND — Analog ground |
| Контакт 14 | AIN2A+ — Channel 2 differential input positive |
| Контакт 15 | AIN2A- — Channel 2 differential input negative |
| Контакт 16 | AIN2B+ — Channel 2 second input positive |
| Контакт 17 | AIN2B- — Channel 2 second input negative |
| Контакт 18 | AGND — Analog ground |
| Контакт 19 | NC — Not connected (per datasheet) |
| Контакт 20 | AVDD — Analog 3.3V supply |
| Контакт 21 | VREFRTN — Voltage reference return |
| Контакт 22 | NC — Not connected (per datasheet) |
| Контакт 23 | DREFC — Data reformatter clock |
| Контакт 24 | DRESET — Data reformatter reset |
| Контакт 25 | CSB — SPI chip-select (active low) |
| Контакт 26 | SCLK — SPI clock |
| Контакт 27 | SDIO — SPI data input/output |
| Контакт 28 | SDO — SPI data output |
| Контакт 29 | OEC — Output edge clock (CMOS/LVDS DDR mode dependent) |
| Контакт 30 | OEB — Output enable (active low) |
| Контакт 31 | LVDS_EN — Output mode select (CMOS or LVDS DDR) |
| Контакт 32 | NC — Not connected (per datasheet) |
| Контакт 33 | DVDD — Digital supply (typically 1.8 V) |
| Контакт 34 | DGND — Digital ground |
| Контакт 35 | D[0] — LVDS/CMOS data output bit 0 |
| Контакт 36 | D[1] — LVDS/CMOS data output bit 1 |
| Контакт 37 | D[2] — LVDS/CMOS data output bit 2 |
| Контакт 38 | D[3] — LVDS/CMOS data output bit 3 |
| Контакт 39 | D[4] — LVDS/CMOS data output bit 4 |
| Контакт 40 | D[5] — LVDS/CMOS data output bit 5 |
| Контакт 41 | D[6] — LVDS/CMOS data output bit 6 |
| Контакт 42 | D[7] — LVDS/CMOS data output bit 7 |
| Контакт 43 | D[8] — LVDS/CMOS data output bit 8 |
| Контакт 44 | D[9] — LVDS/CMOS data output bit 9 |
| Контакт 45 | D[10] — LVDS/CMOS data output bit 10 |
| Контакт 46 | D[11] — LVDS/CMOS data output bit 11 |
| Контакт 47 | D[12] — LVDS/CMOS data output bit 12 |
| Контакт 48 | D[13] — LVDS/CMOS data output bit 13 |
| Контакт 49 | DCO+ — Differential data clock output (positive) |
| Контакт 50 | DCO- — Differential data clock output (negative) |
| Контакт 51 | D[14] — Reserved/extended bit (per datasheet) |
| Контакт 52 | D[15] — Reserved/extended bit (per datasheet) |
| Контакт 53 | NC — Not connected (per datasheet) |
| Контакт 54 | DGND — Digital ground |
| Контакт 55 | DVDD — Digital supply (typically 1.8 V) |
| Контакт 56 | NC — Not connected (per datasheet) |
| Контакт 57 | OTR — Out-of-range indicator |
| Контакт 58 | PD — Power-down (active high) |
| Контакт 59 | RESET — Device reset (active high) |
| Контакт 60 | AVDD — Analog 3.3V supply |
| Контакт 61 | NC — Not connected (per datasheet) |
| Контакт 62 | NC — Not connected (per datasheet) |
| Контакт 63 | AGND — Analog ground (also exposed pad) |
| Контакт 64 | EP — Exposed pad (connect to AGND) |
Типичное применение
ADC1412D080HN-C1 подходит для 6 применениеs: Multi-Carrier Cellular Base Station Receiver, Software-Defined Radio Baseband Digitizer, Medical Imaging Ultrasound Receiver, Radar / Lidar Receiver Front-End, Digital Storage Oscilloscope Front-End, Industrial Process-Control Data Acquisition.
Multi-Carrier Cellular Base Station Receiver
The ADC1412D080HN-C1's 80 MSPS sampling on each of its two inputs lets it digitize two adjacent RF downconverter branches simultaneously, enabling diversity reception in macro-cell base stations. Its LVDS DDR output mode places two data bits per clock cycle on a low-swing differential bus, which minimizes board-level EMI between the radio card and the baseband ASIC. The 14-bit resolution is sufficient for 4G LTE receivers where the analog front-end dominates noise. Compared to a sigma-delta ADC, this pipelined part provides lower latency, ideal for closed-loop predistortion paths.
Рекомендуется
Software-Defined Radio Baseband Digitizer
In SDR designs the ADC1412D080HN-C1 digitizes the I and Q baseband signals at 80 MSPS per channel, providing 40 MHz of useful Nyquist bandwidth per branch. The selectable LVDS DDR output mode cuts the FPGA-side pin count by half versus parallel CMOS, simplifying board routing between the ADC and devices such as the XC7A35T-2FTG256I. The pipelined architecture keeps latency in the 10-cycle range, low enough for protocol-aware demodulation. Its 64-pin HVQFN footprint shares the same land pattern as the ADC1412D125HN-C1, allowing design teams to swap in a higher-bandwidth part with no PCB rework.
Рекомендуется
Medical Imaging Ultrasound Receiver
The ADC1412D080HN-C1's dual 14-bit 80 MSPS channels suit mid-range ultrasound beamformer boards where multiple receive channels must digitize time-aligned echoes. The device's pipelined architecture provides deterministic conversion latency, which preserves the delicate beam-focal timing required for image reconstruction. Two matched converters inside one package track each other over temperature better than dual-discrete ADC layouts, supporting consistent image quality from -40C to +85C. The HVQFN-64 package's 9x9 mm area allows very high-density arrays of these converters across dozens of receive channels.
Рекомендуется
Radar / Lidar Receiver Front-End
The ADC1412D080HN-C1 samples two I/Q baseband outputs from a radar or lidar receiver at 80 MSPS, supporting time-domain digitization of returns for moving-target indication. Its 14-bit dynamic range supports the SNR required for FMCW radar detection at ranges below 200 m, while the 80 MSPS rate accommodates chirp bandwidths above 40 MHz. The LVDS DDR interface lands cleanly on FPGAs like the XC6SLX9-2FTG256I used in compact radar boards. The industrial -40C to +85C rating covers outdoor deployed sensor housings.
Рекомендуется
Digital Storage Oscilloscope Front-End
Bench and portable oscilloscopes in the 100 MHz-bandwidth class use the ADC1412D080HN-C1 to simultaneously sample two input channels at 80 MSPS, providing 40 MHz of -3 dB bandwidth per channel. The pipelined latency in the 10-conversion-cycle range enables deep triggers and accurate time-base measurement. Each ADC provides an independent internal reference and bias network, simplifying the bill of materials for multi-channel oscilloscope front-ends. Designers can scale from 2-channel to higher-channel counts by using multiple ADC1412D080HN-C1 parts that share the same package footprint.
Рекомендуется
Industrial Process-Control Data Acquisition
Programmable Logic Controllers and industrial DAQ modules use the ADC1412D080HN-C1 to digitize two high-speed sensor inputs (e.g., vibration and current) on each module slot. The dual 14-bit 80 MSPS channels give 76 dB of dynamic range per measurement, sufficient for precision motor-control feedback loops. The HVQFN-64 footprint keeps the module wide enough to host 4-8 channels per inch of PCB length, improving channel density per rack. Industrial-grade -40C to +85C operation matches factory-floor temperature swings, and the SPI configuration interface simplifies firmware-driven calibration.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для ADC1412D080HN-C1 — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | ADC1412D125HN-C1 | ADC1412D065HN-C1 | ADC1412D080HN/C1,5 | ADC1413S125HN-C1 | ADC1112D125HN-C18 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 64-VFQFPN / HVQFN-64 (9x9 mm) | 64-VFQFPN / HVQFN-64 (9x9 mm) - same | 64-VFQFPN / HVQFN-64 (9x9 mm) - same | 64-VFQFPN / HVQFN-64 (9x9 mm) - same | 64-HVQFN (9x9 mm) - same family | 64-HVQFN (9x9 mm) - same family | 64-HVQFN (9x9 mm) - same family |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits | 11 bits | 10 bits |
| Sample Rate | 80 MSPS | 125 MSPS (+56%) | 65 MSPS (-19%) | 80 MSPS | 125 MSPS (+56%) | 125 MSPS (+56%) | 80 MSPS |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 2 (dual) | 2 (dual) |
| Digital Output | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Param Match (drop-in) | 100% | 90% | 90% | 100% | 80% | 70% | 70% |
Ключевые отличия
- Higher throughput in same package (против ADC1412D065HN-C1)
- Dual-channel simultaneous sampling (против ADC1413S125HN-C1)
- Higher resolution than the 10-bit family variant (против ADC1012D080HN/C1:5)
Заметки по проектированию
Estimated: Power consumption scales linearly with sample rate; at 80 MSPS this Renesas ADC1412D family device typically draws around 600-700 mW from AVDD plus around 100-150 mW from DVDD depending on output mode. Place a ferrite bead on the analog supply rail followed by 10uF tantalum and 0.1uF ceramic decoupling directly at each AVDD pin; isolate from the noisy digital supply with a separate LDO regulator.
The 64-VFQFPN (HVQFN-64, 9x9 mm, 0.85 mm height) package requires a small land pattern - refer to Renesas application notes for HVQFN PCB layout recommendations, including micro-via arrays under the exposed pad to a continuous analog ground pour. Recommended stack-up: top routing layer for analog signals, layer-2 continuous AGND plane for the ADC footprint, layer-3 DGND isolated under digital outputs only. This minimizes digital return current coupling into the analog inputs.
Drive the analog inputs with a low-noise differential amplifier (such as an FDA) and DC-couple them to the desired common-mode voltage per datasheet; mismatched impedance between AIN+ and AIN- directly degrades SFDR and ENOB. When switching from CMOS mode to LVDS DDR mode the PCB footprint is unchanged but the FPGA side must reconfigure its DCO skew calibration and IDDR capture registers. Verify timing against the latest datasheet timing diagrams before re-spinning the board.
Информация о соответствии
Compliance flags not present in verified web data; review the Renesas product environmental compliance statement before RoHS/REACH declaration. ADC1412D080HN-C1 is marked Obsolete per the Renesas website.
