ADC1412D080HN-C1 - Dual 14-bit 80MSPS ADC | Renesas
料号： ADC1412D080HN-C1 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $44.2 | $442.00 |
| 100 | $39.8 | $3,980.00 |
| 500 | $35.6 | $17,800.00 |
| 1,000 | $31.9 | $31,900.00 |
ADC1412D080HN-C1 概述
An ADC (Analog-to-Digital Converter) is a data acquisition integrated circuit that converts continuous-time analog signals into discrete digital codes, enabling downstream processing by microcontrollers, FPGAs, or DSPs. In the broader taxonomy, the ADC1412D080HN-C1 belongs to the class of pipeline ADCs, which interleave sub-ADCs and DACs to achieve high sample rates (the pipeline architecture -> successive-approximation/pipelined/sigma-delta ADC -> data converter -> data acquisition IC -> analog mixed-signal IC hierarchy). This topology delivers the best throughput-to-power trade-off in the 50-200 MSPS range.
Key features include 14-bit resolution, 80 MSPS sampling rate, dual-channel simultaneous sampling, configurable CMOS or LVDS DDR output interface, and an industrial temperature range of -40C to +85C. The device supports a 3-wire SPI-compatible serial interface for configuration. The HVQFN-64 (9x9 mm) package has low thermal resistance and is suitable for high-density PCB layouts common in communications infrastructure equipment.
The pipelined architecture uses a switched-capacitor front-end and digital error-correction logic, achieving low latency and high spurious-free dynamic range. The device requires an external reference and an external analog input driver, and the LVDS DDR mode minimizes the digital output bus width while preserving the 80 MSPS throughput, simplifying board-level routing between the ADC and the downstream FPGA receiver.
Typical applications include multi-carrier cellular base stations, radar and lidar receiver front-ends, medical imaging digitizers, and high-end oscilloscopes or spectrum analyzers. The Renesas ADC1412D125HN-C1 (125 MSPS) and ADC1412D065HN-C1 (65 MSPS) variants cover the same application space at different sampling rates, all sharing the HVQFN-64 (9x9) footprint for design scalability.
When designing with this device, prioritize proper grounding and power-rail decoupling; Renesas application briefs recommend a clean analog supply with a ferrite bead plus a 10uF/0.1uF capacitor stack on the AVDD pin. Note that the manufacturer marks this part Obsolete per Renesas documentation, so procurement should plan long lead times or evaluate current production parts from the ADC1412D family.
This page consolidates distributor pricing, same-package drop-in alternatives, and design guidance beyond what is in the standalone Renesas datasheet, helping engineers source and integrate the ADC1412D080HN-C1 efficiently.
直接替换替代料： ADC1412D080HN-C1 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC1412D080HN-C1 （相同外形与封装尺寸） ——差异在于 Package, Resolution, Number of Channels, Input Type, Sampling Rate.
快速对比工具——选择替代料号进行并排对比：
ADC1412D125HN-C1
✅ 直接替换📋 参考替代料（不在目录中）
ADC1412D065HN-C1
✅ 直接替换✓ 有现货
$21.45 / 个
查看数据手册 →ADC1412D080HN/C1,5
✅ 直接替换📋 参考替代料（不在目录中）
ADC1413S125HN-C1
✅ 直接替换✓ 有现货
$21.3 / 个
查看数据手册 →ADC1112D125HN-C18
✅ 直接替换✓ 有现货
$9.48 / 个
查看数据手册 →ADC1012D080HN/C1:5
✅ 直接替换✓ 有现货
$12.1 / 个
查看数据手册 →ADC1412D080HN-C1 最大额定值与电气特性
| 分辨率 | 14 bits |
| Number of Input Channels | 2 (dual, simultaneous sampling) |
| 采样率 | 80 MSPS |
| Architecture | Pipelined |
| Input Type | Differential analog inputs |
| Digital Output Interface | CMOS or LVDS DDR (selectable) |
| Configuration Interface | 3-wire SPI-compatible serial |
| Input Clock | Sample-rate dependent, single-ended or differential clock input |
| Supply Voltage (AVDD) | 3.3 V (per package datasheet family) |
| 工作温度 | -40C to +85C (industrial grade) |
| 封装 | 64-VFQFPN / HVQFN-64 (9x9 mm, 0.85 mm height, SOT804-6) |
| 引脚数量 | 64 |
| 安装类型 | Surface Mount |
| Screening Level | Industrial |
ADC1412D080HN-C1 引脚配置
| 引脚 1 | CLK+ — Differential clock input (positive) |
| 引脚 2 | CLK- — Differential clock input (negative) |
| 引脚 3 | NC — Not connected (per datasheet) |
| 引脚 4 | AVDD — Analog 3.3V supply |
| 引脚 5 | VREFIN — Voltage reference input |
| 引脚 6 | AGND — Analog ground |
| 引脚 7 | AIN1A+ — Channel 1 differential input positive |
| 引脚 8 | AIN1A- — Channel 1 differential input negative |
| 引脚 9 | AIN1B+ — Channel 1 second input positive |
| 引脚 10 | AIN1B- — Channel 1 second input negative |
| 引脚 11 | NC — Not connected (per datasheet) |
| 引脚 12 | AVDD — Analog 3.3V supply |
| 引脚 13 | AGND — Analog ground |
| 引脚 14 | AIN2A+ — Channel 2 differential input positive |
| 引脚 15 | AIN2A- — Channel 2 differential input negative |
| 引脚 16 | AIN2B+ — Channel 2 second input positive |
| 引脚 17 | AIN2B- — Channel 2 second input negative |
| 引脚 18 | AGND — Analog ground |
| 引脚 19 | NC — Not connected (per datasheet) |
| 引脚 20 | AVDD — Analog 3.3V supply |
| 引脚 21 | VREFRTN — Voltage reference return |
| 引脚 22 | NC — Not connected (per datasheet) |
| 引脚 23 | DREFC — Data reformatter clock |
| 引脚 24 | DRESET — Data reformatter reset |
| 引脚 25 | CSB — SPI chip-select (active low) |
| 引脚 26 | SCLK — SPI clock |
| 引脚 27 | SDIO — SPI data input/output |
| 引脚 28 | SDO — SPI data output |
| 引脚 29 | OEC — Output edge clock (CMOS/LVDS DDR mode dependent) |
| 引脚 30 | OEB — Output enable (active low) |
| 引脚 31 | LVDS_EN — Output mode select (CMOS or LVDS DDR) |
| 引脚 32 | NC — Not connected (per datasheet) |
| 引脚 33 | DVDD — Digital supply (typically 1.8 V) |
| 引脚 34 | DGND — Digital ground |
| 引脚 35 | D[0] — LVDS/CMOS data output bit 0 |
| 引脚 36 | D[1] — LVDS/CMOS data output bit 1 |
| 引脚 37 | D[2] — LVDS/CMOS data output bit 2 |
| 引脚 38 | D[3] — LVDS/CMOS data output bit 3 |
| 引脚 39 | D[4] — LVDS/CMOS data output bit 4 |
| 引脚 40 | D[5] — LVDS/CMOS data output bit 5 |
| 引脚 41 | D[6] — LVDS/CMOS data output bit 6 |
| 引脚 42 | D[7] — LVDS/CMOS data output bit 7 |
| 引脚 43 | D[8] — LVDS/CMOS data output bit 8 |
| 引脚 44 | D[9] — LVDS/CMOS data output bit 9 |
| 引脚 45 | D[10] — LVDS/CMOS data output bit 10 |
| 引脚 46 | D[11] — LVDS/CMOS data output bit 11 |
| 引脚 47 | D[12] — LVDS/CMOS data output bit 12 |
| 引脚 48 | D[13] — LVDS/CMOS data output bit 13 |
| 引脚 49 | DCO+ — Differential data clock output (positive) |
| 引脚 50 | DCO- — Differential data clock output (negative) |
| 引脚 51 | D[14] — Reserved/extended bit (per datasheet) |
| 引脚 52 | D[15] — Reserved/extended bit (per datasheet) |
| 引脚 53 | NC — Not connected (per datasheet) |
| 引脚 54 | DGND — Digital ground |
| 引脚 55 | DVDD — Digital supply (typically 1.8 V) |
| 引脚 56 | NC — Not connected (per datasheet) |
| 引脚 57 | OTR — Out-of-range indicator |
| 引脚 58 | PD — Power-down (active high) |
| 引脚 59 | RESET — Device reset (active high) |
| 引脚 60 | AVDD — Analog 3.3V supply |
| 引脚 61 | NC — Not connected (per datasheet) |
| 引脚 62 | NC — Not connected (per datasheet) |
| 引脚 63 | AGND — Analog ground (also exposed pad) |
| 引脚 64 | EP — Exposed pad (connect to AGND) |
典型应用
ADC1412D080HN-C1 适用于 6 应用s: Multi-Carrier Cellular Base Station Receiver, Software-Defined Radio Baseband Digitizer, Medical Imaging Ultrasound Receiver, Radar / Lidar Receiver Front-End, Digital Storage Oscilloscope Front-End, Industrial Process-Control Data Acquisition.
Multi-Carrier Cellular Base Station Receiver
The ADC1412D080HN-C1's 80 MSPS sampling on each of its two inputs lets it digitize two adjacent RF downconverter branches simultaneously, enabling diversity reception in macro-cell base stations. Its LVDS DDR output mode places two data bits per clock cycle on a low-swing differential bus, which minimizes board-level EMI between the radio card and the baseband ASIC. The 14-bit resolution is sufficient for 4G LTE receivers where the analog front-end dominates noise. Compared to a sigma-delta ADC, this pipelined part provides lower latency, ideal for closed-loop predistortion paths.
推荐
Software-Defined Radio Baseband Digitizer
In SDR designs the ADC1412D080HN-C1 digitizes the I and Q baseband signals at 80 MSPS per channel, providing 40 MHz of useful Nyquist bandwidth per branch. The selectable LVDS DDR output mode cuts the FPGA-side pin count by half versus parallel CMOS, simplifying board routing between the ADC and devices such as the XC7A35T-2FTG256I. The pipelined architecture keeps latency in the 10-cycle range, low enough for protocol-aware demodulation. Its 64-pin HVQFN footprint shares the same land pattern as the ADC1412D125HN-C1, allowing design teams to swap in a higher-bandwidth part with no PCB rework.
推荐
Medical Imaging Ultrasound Receiver
The ADC1412D080HN-C1's dual 14-bit 80 MSPS channels suit mid-range ultrasound beamformer boards where multiple receive channels must digitize time-aligned echoes. The device's pipelined architecture provides deterministic conversion latency, which preserves the delicate beam-focal timing required for image reconstruction. Two matched converters inside one package track each other over temperature better than dual-discrete ADC layouts, supporting consistent image quality from -40C to +85C. The HVQFN-64 package's 9x9 mm area allows very high-density arrays of these converters across dozens of receive channels.
推荐
Radar / Lidar Receiver Front-End
The ADC1412D080HN-C1 samples two I/Q baseband outputs from a radar or lidar receiver at 80 MSPS, supporting time-domain digitization of returns for moving-target indication. Its 14-bit dynamic range supports the SNR required for FMCW radar detection at ranges below 200 m, while the 80 MSPS rate accommodates chirp bandwidths above 40 MHz. The LVDS DDR interface lands cleanly on FPGAs like the XC6SLX9-2FTG256I used in compact radar boards. The industrial -40C to +85C rating covers outdoor deployed sensor housings.
推荐
Digital Storage Oscilloscope Front-End
Bench and portable oscilloscopes in the 100 MHz-bandwidth class use the ADC1412D080HN-C1 to simultaneously sample two input channels at 80 MSPS, providing 40 MHz of -3 dB bandwidth per channel. The pipelined latency in the 10-conversion-cycle range enables deep triggers and accurate time-base measurement. Each ADC provides an independent internal reference and bias network, simplifying the bill of materials for multi-channel oscilloscope front-ends. Designers can scale from 2-channel to higher-channel counts by using multiple ADC1412D080HN-C1 parts that share the same package footprint.
推荐
Industrial Process-Control Data Acquisition
Programmable Logic Controllers and industrial DAQ modules use the ADC1412D080HN-C1 to digitize two high-speed sensor inputs (e.g., vibration and current) on each module slot. The dual 14-bit 80 MSPS channels give 76 dB of dynamic range per measurement, sufficient for precision motor-control feedback loops. The HVQFN-64 footprint keeps the module wide enough to host 4-8 channels per inch of PCB length, improving channel density per rack. Industrial-grade -40C to +85C operation matches factory-floor temperature swings, and the SPI configuration interface simplifies firmware-driven calibration.
推荐
推荐产品汇总
工程参考数据： ADC1412D080HN-C1 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1412D125HN-C1 | ADC1412D065HN-C1 | ADC1412D080HN/C1,5 | ADC1413S125HN-C1 | ADC1112D125HN-C18 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 64-VFQFPN / HVQFN-64 (9x9 mm) | 64-VFQFPN / HVQFN-64 (9x9 mm) - same | 64-VFQFPN / HVQFN-64 (9x9 mm) - same | 64-VFQFPN / HVQFN-64 (9x9 mm) - same | 64-HVQFN (9x9 mm) - same family | 64-HVQFN (9x9 mm) - same family | 64-HVQFN (9x9 mm) - same family |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits | 11 bits | 10 bits |
| Sample Rate | 80 MSPS | 125 MSPS (+56%) | 65 MSPS (-19%) | 80 MSPS | 125 MSPS (+56%) | 125 MSPS (+56%) | 80 MSPS |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 2 (dual) | 2 (dual) |
| Digital Output | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Param Match (drop-in) | 100% | 90% | 90% | 100% | 80% | 70% | 70% |
关键差异点
- Higher throughput in same package （对比 ADC1412D065HN-C1)
- Dual-channel simultaneous sampling （对比 ADC1413S125HN-C1)
- Higher resolution than the 10-bit family variant （对比 ADC1012D080HN/C1:5)
设计说明
Estimated: Power consumption scales linearly with sample rate; at 80 MSPS this Renesas ADC1412D family device typically draws around 600-700 mW from AVDD plus around 100-150 mW from DVDD depending on output mode. Place a ferrite bead on the analog supply rail followed by 10uF tantalum and 0.1uF ceramic decoupling directly at each AVDD pin; isolate from the noisy digital supply with a separate LDO regulator.
The 64-VFQFPN (HVQFN-64, 9x9 mm, 0.85 mm height) package requires a small land pattern - refer to Renesas application notes for HVQFN PCB layout recommendations, including micro-via arrays under the exposed pad to a continuous analog ground pour. Recommended stack-up: top routing layer for analog signals, layer-2 continuous AGND plane for the ADC footprint, layer-3 DGND isolated under digital outputs only. This minimizes digital return current coupling into the analog inputs.
Drive the analog inputs with a low-noise differential amplifier (such as an FDA) and DC-couple them to the desired common-mode voltage per datasheet; mismatched impedance between AIN+ and AIN- directly degrades SFDR and ENOB. When switching from CMOS mode to LVDS DDR mode the PCB footprint is unchanged but the FPGA side must reconfigure its DCO skew calibration and IDDR capture registers. Verify timing against the latest datasheet timing diagrams before re-spinning the board.
合规信息
Compliance flags not present in verified web data; review the Renesas product environmental compliance statement before RoHS/REACH declaration. ADC1412D080HN-C1 is marked Obsolete per the Renesas website.
