EP1810GC-35 vs EP1810JC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GC-35 sa pamamagitan ng Altera at EP1810JC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810GC-35 EP1810JC-25
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili NRND
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Family Altera Classic EPLD —
Technology CMOS, UV-erasable EPROM cells CMOS, UV-erasable (windowed ceramic DIP)
Packhaging CPGA-68 (Ceramic Pin Grid Array, 68-pin) 28-pin ceramic DIP (J) with quartz window
Bilang ng Pins 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40 °C to 85 °C (industrial, per distributor listings)
Volte ng Pagbibigay [DATA_NEEDED: VCC range] —
Uri ng Pagpapasok Through Hole Through-hole
Tindminan RoHS Not applicable (legacy ceramic package) [DATA_NEEDED: RoHS compliance status]
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — Altera/Intel Classic EPLD (EP1810 series)
Propagation Delay (tPD) — 25 ns
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
Dedicated Inputs — 12
External Clock Inputs — 4
Supply Voltage (VCC) — 4.75 V to 5.25 V
Erasure Method — UV light (windowed package)
Katayuan ng Lifecycle — NRND (Not Recommended for New Designs)

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