EP1810GC-35 vs EP1810LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GC-35 sa pamamagitan ng Altera at EP1810LC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GC-35 | EP1810LC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | CMOS, low-power (LC) |
| Packhaging | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Bilang ng Pins | 68 | 68 |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | 48 |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: temperature grade] |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | 5 V (typical) |
| Uri ng Pagpapasok | Through Hole | — |
| Tindminan RoHS | Not applicable (legacy ceramic package) | unknown (legacy ceramic package) |
| Lead-Free Status | Not applicable | — |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |