EP1810GI-45 vs EP1810JC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GI-45 sa pamamagitan ng Altera at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GI-45 | EP1810JC-45 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | EP1810 (Classic EPLD Family) |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-erasable |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Bilang ng Pin | 68 | 68 |
| Uri ng Pagpapasok | Through-Hole | Surface Mount |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| Tindminan RoHS | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Lead-Free | No | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Maksimum na Taktiko ng Oras | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Packhaging | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |