EP1810GI-45 vs EP1810JC-45 比較
詳細並排比較 EP1810GI-45 由 Altera 與 EP1810JC-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GI-45 | EP1810JC-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | EP1810 (Classic EPLD Family) |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-erasable |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| 腳位數 | 68 | 68 |
| 安裝類型 | Through-Hole | Surface Mount |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS 狀態 | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Lead-Free | No | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| 最大時脈頻率 | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| 封裝 | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |