EP1810GM883B vs EP1810JM-45 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GM883B sa pamamagitan ng Altera at EP1810JM-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810GM883B EP1810JM-45
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family EP1810 (Classic EPLD) Classic EPLD (EP1810 series)
Macrocells 48 48
User Flip-Flops Up to 64 —
Total Inputs 60 —
Dedicated Inputs 12 —
I/O Pins 48 (bidirectional, tri-state) —
Propagation Delay (tPD) 50 ns max —
Supply Voltage (VCC) 4.5 V to 5.5 V 4.5 V to 5.5 V
Technology CMOS, UV-erasable CMOS, UV-EPROM configuration
Temperature na Operasyon -55 °C to +125 °C (Military, MIL-STD-883B) -55 C to +125 C (military grade)
Package Type Ceramic Pin Grid Array (PGA), 84 pins JLCC-68 (ceramic J-leaded chip carrier)
Package Designator GM (ceramic PGA) —
Processing Level MIL-STD-883B (Class B) —
Programming Method UV-erasable / Altera programming hardware —
Uri ng Pagpapasok Through-hole (PGA socket or PCB through-hole) Surface Mount (J-lead)
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Logic Family TTL-compatible I/O —
Usable Gates — ~900 gates
Propagation Delay (tpd) — 45 ns (max, -45 speed grade)
Package Code — JM (windowed ceramic, UV-erasable)
Bilang ng Pin — 68
I/O Compatibility — CMOS / TTL
Configuration Method — JEDEC fuse map, EPROM programmer
Programming Technology — UV-erasable EPROM (non-volatile, instant-on)
Logic Type — EPLD / PLD (programmable logic device)
Tindminan RoHS — [DATA_NEEDED: RoHS status - legacy mil-spec part]
Level ng MSL — [DATA_NEEDED: MSL level]

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita