EP1810JC-25 vs EP1810JC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-25 sa pamamagitan ng Intel at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JC-25 | EP1810JC-45 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera/Intel Classic EPLD (EP1810 series) | EP1810 (Classic EPLD Family) |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperature na Operasyon | -40 °C to 85 °C (industrial, per distributor listings) | — |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS, UV-erasable |
| Packhaging | 28-pin ceramic DIP (J) with quartz window | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Uri ng Pagpapasok | Through-hole | Surface Mount |
| Erasure Method | UV light (windowed package) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Katayuan ng Lifecycle | NRND (Not Recommended for New Designs) | — |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Maksimum na Taktiko ng Oras | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Bilang ng Pin | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |