EP1810JC35 vs EP1810JC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC35 sa pamamagitan ng Altera at EP1810JC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JC35 EP1810JC-25
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Altera Classic EPLD Altera/Intel Classic EPLD (EP1810 series)
Product Type UV-erasable / OTP Complex PLD (EPLD) Classic EPLD (Erasable Programmable Logic Device)
Macrocells 48 48
Logic Gates (typ.) [DATA_NEEDED: logic gates count] —
Maximum User I/O Pins [DATA_NEEDED: user I/O count for PLCC-68] —
Propagation Delay (tPD) 35 ns 25 ns
Maksimum na Taktiko ng Oras 40 MHz —
Supply Voltage (VCC max) 5.25 V —
Supply Voltage (VCC min) [DATA_NEEDED: VCC minimum] —
Process Technology CMOS EPROM cell —
Temperature na Operasyon 0 C to +70 C (Commercial) -40 °C to 85 °C (industrial, per distributor listings)
Packhaging PLCC-68 (J-lead, ceramic) 28-pin ceramic DIP (J) with quartz window
Package Code QCCJ —
Terminal Form J-BEND —
Number of Terminals 68 —
Programming UV-erase (windowed) or OTP —
Development Tool Altera MAX+plus II / A+plus —
Tindminan RoHS [DATA_NEEDED: RoHS compliance for EP1810JC35] [DATA_NEEDED: RoHS compliance status]
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
Dedicated Inputs — 12
External Clock Inputs — 4
Supply Voltage (VCC) — 4.75 V to 5.25 V
Technology — CMOS, UV-erasable (windowed ceramic DIP)
Uri ng Pagpapasok — Through-hole
Erasure Method — UV light (windowed package)
Katayuan ng Lifecycle — NRND (Not Recommended for New Designs)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita