EP1810JC35 vs EP1810JC-25 Karşılaştırma
Ayrıntılı yan yana karşılaştırma EP1810JC35 tarafından Altera ve EP1810JC-25 tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.
Özellik Karşılaştırması
| Parametre | EP1810JC35 | EP1810JC-25 |
|---|---|---|
| Marka | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Yaşam Döngüsü Durumu | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera/Intel Classic EPLD (EP1810 series) |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | 48 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Azami Saat Hızı | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| İşletim Sıcaklığı | 0 C to +70 C (Commercial) | -40 °C to 85 °C (industrial, per distributor listings) |
| Paket | PLCC-68 (J-lead, ceramic) | 28-pin ceramic DIP (J) with quartz window |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS Durumu | [DATA_NEEDED: RoHS compliance for EP1810JC35] | [DATA_NEEDED: RoHS compliance status] |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Technology | — | CMOS, UV-erasable (windowed ceramic DIP) |
| Montaj Türü | — | Through-hole |
| Erasure Method | — | UV light (windowed package) |
| Yaşam Döngüsü Durumu | — | NRND (Not Recommended for New Designs) |