EP1810JI-35 vs EP1810JC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-35 sa pamamagitan ng Intel at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JI-35 | EP1810JC-45 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Packhaging | 28-pin JLCC (J-leaded ceramic, windowed) | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Volte ng Pagbibigay | 5 V (typical classic EPLD) | — |
| Programmability | UV-erase, windowed for lab reprogram | — |
| Uri ng Pagpapasok | Through-Hole (J-lead) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Maksimum na Taktiko ng Oras | — | 33.3 MHz |
| Technology | — | CMOS, UV-erasable |
| Maximum Supply Voltage | — | 5.25 V |
| Bilang ng Pin | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |