EP1810JI-45 vs EP1810JC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-45 sa pamamagitan ng Altera at EP1810JC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JI-45 EP1810JC-25
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Manufacturer Altera (now Intel FPGA) —
Series Classic EPLD Family —
Device Type UV-Erasable / OTP Complex PLD —
Macrocell Count 48 —
Maximum Operating Frequency 33.3 MHz —
Propagation Delay (tPD) 50 ns 25 ns
Configurable I/O Lines 48 —
Dedicated Inputs 12 12
Technology CMOS EPROM CMOS, UV-erasable (windowed ceramic DIP)
Package Code QCCJ —
Package Type 68-pin JLCC (J-leaded ceramic chip carrier) —
Terminal Form J BEND —
Package Shape SQUARE —
Number of Terminals 68 —
Temperature Grade INDUSTRIAL —
Temperature na Operasyon -40 °C to +85 °C -40 °C to 85 °C (industrial, per distributor listings)
Volte ng Pagbibigay 5 V (TTL compatible) —
Programming Method UV-erase (windowed) / OTP via JEDEC —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — Altera/Intel Classic EPLD (EP1810 series)
Macrocells — 48
Maximum Toggle Frequency — [DATA_NEEDED: max fMAX]
Input Lines — 60 (including I/O)
I/O Lines — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 4.75 V to 5.25 V
Packhaging — 28-pin ceramic DIP (J) with quartz window
Uri ng Pagpapasok — Through-hole
Erasure Method — UV light (windowed package)
Tindminan RoHS — [DATA_NEEDED: RoHS compliance status]
Katayuan ng Lifecycle — NRND (Not Recommended for New Designs)

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