EP1810JI-45 vs EP1810JC-25 比較
詳細並排比較 EP1810JI-45 由 Altera 與 EP1810JC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JI-45 | EP1810JC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | 25 ns |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| Technology | CMOS EPROM | CMOS, UV-erasable (windowed ceramic DIP) |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| 工作溫度 | -40 °C to +85 °C | -40 °C to 85 °C (industrial, per distributor listings) |
| 供應電壓 | 5 V (TTL compatible) | — |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera/Intel Classic EPLD (EP1810 series) |
| Macrocells | — | 48 |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| 封裝 | — | 28-pin ceramic DIP (J) with quartz window |
| 安裝類型 | — | Through-hole |
| Erasure Method | — | UV light (windowed package) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance status] |
| 生命週期狀態 | — | NRND (Not Recommended for New Designs) |