EP1810JM-45 vs EP1810JC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JM-45 sa pamamagitan ng Altera at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JM-45 | EP1810JC-45 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 48 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | CMOS, UV-erasable |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | — |
| Package Code | JM (windowed ceramic, UV-erasable) | QCCJ |
| Bilang ng Pin | 68 | 68 |
| Temperature na Operasyon | -55 C to +125 C (military grade) | — |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Uri ng Pagpapasok | Surface Mount (J-lead) | Surface Mount |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Maksimum na Taktiko ng Oras | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Packhaging | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Temperature Grade | — | Commercial |