EP1810LC-35 vs EP1810JC-45 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-35 sa pamamagitan ng Rochester Electronics at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Rochester Electronics
EP1810LC-35 EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP1810LC-35 EP1810JC-45
Brand Rochester Electronics Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili NRND
Device Type EPLD (Erasable Programmable Logic Device) —
Series Classic EP1810 —
Macrocells 48 48
Equivalent Gates 900 usable / 2100 equivalent 2100 gates
Maximum Operating Frequency 28.6 MHz —
Propagation Delay (tpd) 35 ns (max, '-35' speed grade) 45 ns
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable
Packhaging 68-pin PLCC (J-Lead) PLCC-68 (QCCJ, J-Lead, windowed ceramic)
Uri ng Pagpapasok Surface Mount (socketable) Surface Mount
Temperature na Operasyon 0C to +70C (commercial) —
I/O Pins [DATA_NEEDED: I/O count exact] 48
Configuration Method UV-erase + EPROM programmer —
Programmable Interconnect Centralized Programmable Interconnect Array (PIA) —
Development Tool (legacy) MAX+PLUS II / A+PLUS —
Tindminan RoHS [DATA_NEEDED] [DATA_NEEDED: RoHS compliance not stated in verified data]
Lead-Free [DATA_NEEDED] —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — EP1810 (Classic EPLD Family)
Dedicated Inputs — 12
Total User I/O — 60
Maksimum na Taktiko ng Oras — 33.3 MHz
Maximum Supply Voltage — 5.25 V
Bilang ng Pin — 68
Package Code — QCCJ
Temperature Grade — Commercial

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