EP1810LC-35T vs EP1810LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-35T sa pamamagitan ng Intel at EP1810LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-35T EP1810LC-25
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family EP1810 Classic EPLD —
Product Type Erasable Programmable Logic Device (EPLD) —
Usable Gates 900 —
Macro Cells 48 —
Pin-to-Pin Delay (tpd) 35 ns —
Maximum Frequency (fmax) 28.6 MHz —
Supply Voltage (Vcc) 5 V —
Technology CMOS CMOS EPLD (erasable programmable logic device)
Logic Compatibility 100% TTL emulation —
Packhaging 68-pin PLCC (Plastic Leaded Chip Carrier) 68-pin JLCC (J-leaded ceramic chip carrier)
Package Suffix T = Tape and Reel —
Temperature na Operasyon 0 C to +70 C (Commercial) [DATA_NEEDED: temperature grade for LC package]
Uri ng Pagpapasok Surface Mount (PLCC socket or direct solder) Surface Mount
Programming Method UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II Altera Classic programmer + MAX+PLUS II legacy flow
Tindminan RoHS Non-compliant (legacy PLCC product) [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Logic Family Replacement Target 74LS low-power Schottky TTL —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Macrocells — 48
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Programmable Interconnect — Global + Local buses
Katayuan ng Lifecycle — Obsolete (legacy Altera Classic family)

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