EP1810LI-25 vs EP1810LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LI-25 sa pamamagitan ng Altera at EP1810LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LI-25 EP1810LC-25
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device), UV-erasable / OTP —
Macrocells 48 48
Usable Gates 900 —
Propagation Delay (tPD) 25 ns 25 ns
Maximum Counter Frequency 40 MHz —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) 5 V (TTL-compatible)
I/O Pins 48 48
Dedicated Inputs 12 12
Global Clock Inputs 4 —
Interconnect Programmable global and local buses —
Packhaging 68-pin PLCC (J68, J-Lead) 68-pin JLCC (J-leaded ceramic chip carrier)
JESD-30 Package Code S-PQCC-J68 —
Process Technology CMOS —
Operating Temperature (Industrial 'I' suffix) -40 C to +85 C —
Programming Mode EPROM/UV-erasable (windowed) and OTP —
Development Tool Altera MAX+PLUS II —
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Lead-Free Status unknown —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
External Clock Inputs — 4
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Uri ng Pagpapasok — Surface Mount
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Katayuan ng Lifecycle — Obsolete (legacy Altera Classic family)
Temperature na Operasyon — [DATA_NEEDED: temperature grade for LC package]

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