EP1S20F672C6 vs EP1S20F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C6 sa pamamagitan ng Altera at EP1S20F672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20F672C6 | EP1S20F672C7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Manufacturer | Altera (now Intel) | — |
| Series | Stratix | Stratix |
| Family | Stratix (first generation) | Altera Stratix FPGA |
| Process Technology | 0.13 µm CMOS | — |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | 1,669,248 |
| Maximum User I/Os | 426 | — |
| Packhaging | 672-ball FineLine BGA | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Package Code | F672 | — |
| Speed Grade | C6 | C7 |
| Temperature na Operasyon | 0°C to +85°C (Commercial) | 0C to 85C (commercial) |
| Volte ng Pagbibigay | Core 1.5 V, I/O programmable | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| User I/O Pins | — | 426 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Logic Family | — | CMOS, SRAM-based |
| Core Supply Voltage | — | 1.5 V |
| Configuration Modes | — | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Clock PLLs | — | Up to 10 |