EP20K200BC356-1 vs EP20K200CB356C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200BC356-1 sa pamamagitan ng Altera at EP20K200CB356C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K200CB356C7N - APEX 20KC FPGA 200K Gates 356-BGA | Intel / Altera
EP20K200CB356C7N ObsoletePagsanggunian na paghahambing
| Parametro | EP20K200BC356-1 | EP20K200CB356C7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Function | APEX-20K Field Programmable Gate Array (FPGA) | — |
| Logic Family | CMOS | — |
| Equivalent System Gates | 200K gates | — |
| Logic Elements / Cells | 8320 | 8,320 |
| Total RAM Bits | 106496 bits | — |
| Maksimum na Taktiko ng Oras | 250 MHz | — |
| Core Supply Voltage | 2.5 V | — |
| User I/O Count | 277 | — |
| Bilang ng Pins | 356 | — |
| Packhaging / Kaso | 356-LBGA | — |
| Package Code | LBGA | — |
| Package Shape | Square | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.22 um | 0.15 um CMOS |
| Propagation Delay (tPD) | 2.5 ns (from -1N variant listing) | — |
| Hanay ng Temperature na Operasyon | 0 to 85 C (commercial, per -1N variant listing) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] | unknown |
| Lead-Free Finish | [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] | — |
| Family | — | APEX 20KC |
| Series | — | EP20K200 |
| System Gates | — | 200,000 |
| Maximum Operating Frequency | — | 3571.6 MHz (internal equivalent) |
| Propagation Delay | — | 1.48 ns |
| User I/Os | — | 263 |
| Input Terminals | — | 267 |
| Supply Voltage (Nominal) | — | 1.8 V |
| Temperature na Operasyon | — | 0C to +85C (Commercial) |
| Packhaging | — | 356-ball PBGA (S-PBGA) |
| Embedded Memory | — | ESBs (dual-port RAM/ROM/FIFO) |
| Clock Management | — | PLL with up to 4 outputs |
| JTAG Support | — | Yes (IEEE 1149.1) |
| In-System Programmable | — | Yes |