EP20K200BC356-1 vs EP20K200CB356C7N 比較

詳細並排比較 EP20K200BC356-1 由 Altera 與 EP20K200CB356C7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K200BC356-1 EP20K200BC356-1 - APEX-20K 200K-Gate FPGA | Altera

EP20K200BC356-1 - APEX-20K 200K-Gate FPGA | Altera

EP20K200BC356-1 Obsolete

規格比較

參數 EP20K200BC356-1 EP20K200CB356C7N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Product Function APEX-20K Field Programmable Gate Array (FPGA) —
Logic Family CMOS —
Equivalent System Gates 200K gates —
Logic Elements / Cells 8320 8,320
Total RAM Bits 106496 bits —
最大時脈頻率 250 MHz —
Core Supply Voltage 2.5 V —
User I/O Count 277 —
腳位數 356 —
封裝 / 外殼 356-LBGA —
Package Code LBGA —
Package Shape Square —
安裝類型 Surface Mount Surface Mount
Process Technology 0.22 um 0.15 um CMOS
Propagation Delay (tPD) 2.5 ns (from -1N variant listing) —
工作溫度範圍 0 to 85 C (commercial, per -1N variant listing) —
RoHS 狀態 [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] unknown
Lead-Free Finish [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] —
Family — APEX 20KC
Series — EP20K200
System Gates — 200,000
Maximum Operating Frequency — 3571.6 MHz (internal equivalent)
Propagation Delay — 1.48 ns
User I/Os — 263
Input Terminals — 267
Supply Voltage (Nominal) — 1.8 V
工作溫度 — 0C to +85C (Commercial)
封裝 — 356-ball PBGA (S-PBGA)
Embedded Memory — ESBs (dual-port RAM/ROM/FIFO)
Clock Management — PLL with up to 4 outputs
JTAG Support — Yes (IEEE 1149.1)
In-System Programmable — Yes

資料表與資源

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