EP20K400FI672-3N vs EP20K400FI672-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-3N sa pamamagitan ng Altera at EP20K400FI672-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FI672-3N | EP20K400FI672-3 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Unknown | Obsolete |
| Device Type | CMOS loadable programmable logic device | — |
| Product Family | APEX 20K | — |
| Series | EP20K400 | EP20K400 |
| Propagation Delay | 3.6 ns | 3.6 ns |
| Maksimum na Taktiko ng Oras | 833 MHz | 833 MHz |
| User I/O Count | 502 | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | 2.375 V to 2.625 V |
| Process Technology | CMOS | CMOS |
| Packhaging | S-PBGA-B672 | — |
| Terminal Count | 672 terminals | 672 |
| Terminal Pitch | 1.000 mm | 1.000 mm |
| Uri ng Pagpapasok | Surface mount | Surface Mount |
| Logic Capacity | [DATA_NEEDED: logic capacity] | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| Tindminan RoHS | unknown | — |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Logic Elements | — | 16640 |
| Total Gates | — | up to 400000 |
| Embedded RAM | — | 212992 bits |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Supply Voltage (Nominal) | — | 2.5 V |
| Package Type | — | PBGA (Plastic BGA) |
| Package Code | — | S-PBGA-B672 |
| Package Shape | — | Square BGA |
| Configuration Interface | — | JTAG (IEEE 1149.1) |
| Level ng MSL | — | 3 |
| Peak Reflow Temperature | — | 220 C |