EP20K400FI672-3N vs EP20K400FI672-3 比較

詳細並排比較 EP20K400FI672-3N 由 Altera 與 EP20K400FI672-3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K400FI672-3N EP20K400FI672-3N - 833 MHz FPGA, 502 I/O, 672-PBGA

EP20K400FI672-3N - 833 MHz FPGA, 502 I/O, 672-PBGA

EP20K400FI672-3N Unknown

規格比較

參數 EP20K400FI672-3N EP20K400FI672-3
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Unknown Obsolete
Device Type CMOS loadable programmable logic device —
Product Family APEX 20K —
Series EP20K400 EP20K400
Propagation Delay 3.6 ns 3.6 ns
最大時脈頻率 833 MHz 833 MHz
User I/O Count 502 —
Nominal Supply Voltage 2.5 V —
Supply Voltage Range 2.375 V to 2.625 V 2.375 V to 2.625 V
Process Technology CMOS CMOS
封裝 S-PBGA-B672 —
Terminal Count 672 terminals 672
Terminal Pitch 1.000 mm 1.000 mm
安裝類型 Surface mount Surface Mount
Logic Capacity [DATA_NEEDED: logic capacity] —
工作溫度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Configuration Method [DATA_NEEDED: configuration method] —
I/O Standard Support [DATA_NEEDED: supported I/O standards] —
RoHS 狀態 unknown —
REACH Status unknown —
AEC-Q100 Qualification unknown —
Family — APEX 20K
Logic Elements — 16640
Total Gates — up to 400000
Embedded RAM — 212992 bits
Maximum User I/O — 502
Dedicated Inputs — 6
Supply Voltage (Nominal) — 2.5 V
Package Type — PBGA (Plastic BGA)
Package Code — S-PBGA-B672
Package Shape — Square BGA
Configuration Interface — JTAG (IEEE 1149.1)
MSL 等級 — 3
Peak Reflow Temperature — 220 C

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